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参数资料
| 型号： | C9726AY |
| 英文描述： | ST92141 - 8/16 BIT MCU FOR 3-PHASE AC MOTOR CONTROL |
| 中文描述： | CPU系统时钟发生器| SSOP封装| 48PIN |塑料 |
| 文件页数： | 2/16页 |
| 文件大小： | 119K |
| 代理商： | C9726AY |
C9726
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07047 Rev. **
05/03/2001
Page 2 of 16
Pin Description
PIN No.
2
Pin Name
REF0 /
CPU_STP#
TYPE
I/O
Description
This is a bi-directional pin with an internal pull-up. The direction of this pin is determined by
the state of signal MODE (pin 7).
If Mode = 0, this pin is a CPU_STP# input pin. When CPU_STP# is asserted low, CPU and
CPU-OD are forced LOW and CPU# is in Tristate.
If Mode = 1, this pin is REF0, a buffer output of the signal applied at Xin.
This is the input pin to the crystal oscillator, which is an internal amplifier. It is typically
connected to a parallel resonant crystal. It may also be driven from an alternative clock
source.
This is the output pin of the crystal oscillator, which is an internal amplifier. It is typically
connected to a parallel resonant crystal. If Xin is driven from an alternative clock source, then
this pin should be unconnected.
This is a power on bi-directional strapping pin with an internal pull-up (see app note, page 4).
During power up, this pin is an input “Mode” for setting the direction of Pin 2. When the power
reaches the rail, this pin becomes a PCI0 clock output.
This is a power on bi-directional strapping pin with an internal pull-up (see app note, page 4).
During power up, this pin is an input “S1” for frequency selection, see table 1, p.1. When the
power reaches the rail, this pin becomes a PCI1 clock output.
PCI clock outputs. Synchronous to CPU clocks.
LVTTL Input pin to the SDRAM(0:12) distribution buffers.
SDRAM Buffered Outputs. They are buffered outputs of the signal applied at SDRAMIN.
When PWR_DN# is low. These signals are forced low regardless of the signal at SDRAMIN.
4
XIN
I
5
XOUT
O
7
PCI0 /
MODE
I/O
8
PCI1 /
S1
I/O
10,11,12,13
15
40,38,37,35,
34,32,31,29,
28,21,20,18,17
23
PCI(2:5)
SDRAMIN
SDRAM (0:12)
OUT
IN
OUT
SDATA
I/O
Serial data input pin. Conforms to the SMBUS specification of a Slave Receiver/Transmitter
device. This pin is an input when receiving data. It is an open drain output when
acknowledging or transmitting. See SMBUS function description, p.8.
Serial clock input pin. Conforms to the SMBUS 100KHz Specification
This is a power on bi-directional strapping pin with an internal pull-down (see app note, page
4). During power up, this pin is an input “S3” for frequency selection, see table 1, p.1. When
the power reaches the rail, this pin becomes a SIO clock output programmed to 24MHz or
48MHz via byte3, bit6 in the SMBUS table. It defaults to 24MHz.
This is a power on bi-directional strapping pin with an internal pull-up (see app note, page 4).
During power up, this pin is an input “S2” for frequency selection, see table 1, p.1. When the
power reaches the rail, this pin becomes a 48MHz, USB clock output.
LVTTL input with an internal pull-up. When this pin is asserted low, the device is in power
down condition, all clocks are stopped in a Low state except CPU# will be in tristate.
Open Drain Differential CPU outputs. They require external pull-up to 1.5V. See table 1 page
1 for frequency selection.
3.3V Host clock output for driving the chipset. It is in phase with CPU clock (pin 43).
This is a power on bi-directional strapping pin with an internal pull-up (see app note, page 4).
During power up, this pin is an input “S0” for frequency selection, see table 1, p.1. When the
power reaches the rail, this pin becomes a REF1, a buffered clock output of the signal applied
at Xin.
Common 3.3V Power Supply.
Power supply for SDRAM. Nominally 3.3V
Ground
24
25
SCLK
24_48MHz / S3
I
I/O
26
48MHz /
S2
I/O
41
PWR_DN#
IN
43, 44
CPU, CPU#
O
46
48
CPUCS
REF1 / S0
O
IN/OUT
1,6,14,27, 42
19, 36, 30
3, 9, 16, 22, 33, 39,
45, 47
VDD
VDDS
VSS
PWR
PWR
GND
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