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| 型号： | C9726AY |
| 英文描述： | ST92141 - 8/16 BIT MCU FOR 3-PHASE AC MOTOR CONTROL |
| 中文描述： | CPU系统时钟发生器| SSOP封装| 48PIN |塑料 |
| 文件页数： | 3/16页 |
| 文件大小： | 119K |
| 代理商： | C9726AY |
C9726
Clock Generator for VIA VT8371/Athlon (K7) Chipset Systems
Approved Product
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07047 Rev. **
05/03/2001
Page 3 of 16
Power on Bi-Directional Pins
Please see App Note AN-0021 for a description on the Power-On Bi-Directional Pins and strapping resistor options
Power Management Functions
Power Management on this device is controlled by CPU_STP# (pin2) and PWR_DN# (pin41).
When CPU_STP# is forced low, all CPU signals are synchronously (no glitch) disabled to a low state and CPU# signals
are in tristate. The CPU_STP# signal does not directly gate the CPU clocks, the CPU clocks will toggle one to three
complete cycles before stopping on a falling edge. When CPU_STP# is released to high, the CPU clocks are
synchronously re-enabled. The clocks will wait the equivalent of one to three cycles after CPU_STP# is asserted high
then will start toggling on the rising edge.
When PWR_DN# is forced low, CPU-OD, CPU, PCI(0:5), SDRAM(0:12), 48MHz, 48_24MHz, and REF(0:1) signals are
synchronously forced low (CPU# is placed in tristate), all internal circuitry (including the crystal buffer) is shutdown and
the device is placed in low power (or in power down) mode. After PWR_DN# is forced low, all power supplies (3.3V and
2.5V) may be removed. All power supplies must be re-applied 200mS before releasing PWR_DN# (to high),
consequently, the device must then be allowed 1mS before the clock outputs settle to their preset frequencies. (see
Fig.1, and table 2 below)
Power Management Timing
PCI(0:5)
PWR_DWN#
CPU
CPU#
Tristate
CPUCS
Fig. 1
All functionality is referenced to the edge of PWR_DN#. If the tss timing is met, with respect to the next occurring PCI_F
low to high transition, then all clocks that are controlled by CPU_STP# are guaranteed to stay low (stopped) or to rise
(run) at the next rising edge of PCI_F. See the AC parameters for tss time. CPU# clocks are stopped in a high state.
Power Management Function Table
CPU_STP#
PWR_DN#
X
0
0
1
1
1
CPUCS
LOW
LOW
RUN
CPU
LOW
LOW
RUN
CPU#
Hi-Z
Hi-Z
RUN
REF(0:1)
LOW
RUN
RUN
PCI(0:5)
LOW
RUN
RUN
48M, 48_24M
LOW
RUN
RUN
SDRAM (0:12)
LOW
RUN
RUN
XTAL, PLLS
OFF
RUN
RUN
Table 2
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