参数资料
型号: CAT150029SWI-GT3
厂商: ON Semiconductor
文件页数: 11/15页
文件大小: 0K
描述: IC SUPERVISOR 2KB SPI EEPR 8SOIC
标准包装: 3,000
类型: 简单复位/加电复位
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 2.93V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
其它名称: 150029SWI-GT3
CAT15002, CAT15004
READ OPERATIONS
Read from Memory Array
To read from memory, the host sends a READ
instruction followed by an 8-bit address (for the
CAT15008, bit 3 of the Read instruction opcode
contains address bit A8).
After receiving the last address bit, the CAT15002/04
will respond by shifting out data on the SO pin (as
shown in Figure 10). Sequentially stored data can be
read out by simply continuing to run the clock. The
internal address pointer is automatically incremented
to the next higher address as data is shifted out. After
Figure 10. READ Timing
CS
ˉˉ
reaching the highest memory address, the address
counter “rolls over” to the lowest memory address, and
the read cycle can be continued indefinitely. The read
operation is terminated by taking CS high.
Read Status Register
To read the status register, the host simply sends a
RDSR command. After receiving the last bit of the
command, the CAT15002/04 will shift out the contents
of the status register on the SO pin (Figure 11). The
status register may be read at any time, including
during an internal write cycle.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SCK
OPCODE
BYTE ADDRESS
SI
0
0
0
0
0
X*
0
1
1
A7 A6 A5
A4
A3
A2
A1 A0
DATA OUT
SO
HIGH IMPEDANCE
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Notes:
* Please check the instruction set table for address
X = 0 for CAT15002; X=A8 for CAT15004
Dashed Line = mode (1, 1) - - - - - -
Figure 11. RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCK
OPCODE
SI
0
0
0
0
0
1
0
1
DATA OUT
SO
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
MSB
Note: Dashed Line = mode (1, 1) - - - - - -
? 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
11
Doc. No. MD-1126 Rev. B
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