参数资料
型号: CAT150029SWI-GT3
厂商: ON Semiconductor
文件页数: 8/15页
文件大小: 0K
描述: IC SUPERVISOR 2KB SPI EEPR 8SOIC
标准包装: 3,000
类型: 简单复位/加电复位
监视电压数目: 1
输出: 推挽式,图腾柱
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 2.93V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 带卷 (TR)
其它名称: 150029SWI-GT3
CAT15002, CAT15004
WRITE OPERATIONS
The CAT15002/04 device powers up into a write disable
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the
memory array or to the status register. In addition, the
address of the memory location(s) to be written must be
outside the protected area, as defined by BP0 and BP1
bits from the status register.
Write Enable and Write Disable
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
instruction to the CAT15002/04. Care must be taken to
Figure 4. WREN Timing
CS
SCK
ˉˉ
take the CS input high after the WREN instruction, as
otherwise the Write Enable Latch will not be properly
set. WREN timing is illustrated in Figure 4. The WREN
instruction must be sent prior any WRITE or WRSR
instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 5. Disabling write
operations by resetting the WEL bit, will protect the
device against inadvertent writes.
SI
0
0
0
0
0
1
1
0
SO
Note: Dashed Line = mode (1, 1) - - - - - -
Figure 5. WRDI Timing
CS
SCK
HIGH IMPEDANCE
SI
0
0
0
0
0
1
0
0
SO
Note: Dashed Line = mode (1, 1) - - - - - -
HIGH IMPEDANCE
Doc. No. MD-1126 Rev. B
8
? 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
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