参数资料
型号: CAT25640VI-GT3
厂商: ON Semiconductor
文件页数: 8/19页
文件大小: 0K
描述: IC EEPROM 64KBIT 10MHZ 8SOIC
标准包装: 1
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 64K (8K x 8)
速度: 20MHz
接口: SPI 3 线串行
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 标准包装
其它名称: CAT25640VI-GT3OSDKR
CAT25640
WRITE OPERATIONS
The CAT25640 device powers up into a write disable
state. The device contains a Write Enable Latch (WEL)
which must be set before attempting to write to the memory
array or to the status register. In addition, the address of the
memory location(s) to be written must be outside the
protected area, as defined by BP0 and BP1 bits from the
status register.
Write Enable and Write Disable
The internal Write Enable Latch and the corresponding
Status Register WEL bit are set by sending the WREN
instruction to the CAT25640. Care must be taken to take the
CS input high after the WREN instruction, as otherwise the
Write Enable Latch will not be properly set. WREN timing
is illustrated in Figure 3. The WREN instruction must be
sent prior to any WRITE or WRSR instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 4. Disabling write
operations by resetting the WEL bit, will protect the device
against inadvertent writes.
CS
SCK
SI
0
0
0
0
0
1
1
0
SO
Dashed Line = mode (1, 1)
HIGH IMPEDANCE
Figure 3. WREN Timing
CS
SCK
SI
0
0
0
0
0
1
0
0
SO
Dashed Line = mode (1, 1)
HIGH IMPEDANCE
Figure 4. WRDI Timing
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