参数资料
| 型号： | CAT93C86VI-GT3 |
| 厂商： | ON Semiconductor |
| 文件页数： | 6/10页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 16KBIT 3MHZ 8SOIC |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 16K（2K x 8 或 1K x 16） |
| 速度： | 3MHz |
| 接口： | Microwire 3 线串行 |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 标准包装 |
| 产品目录页面： | 807 (CN2011-ZH PDF) |
| 其它名称： | CAT93C86VI-GT3DKR |
CAT93C86
Erase
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
t CSMIN . The falling edge of CS will start the self clocking
clear cycle of the selected memory location. The clocking of
the SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the CAT93C86
can be determined by selecting the device and polling the
DO pin. Once cleared, the content of a cleared location
returns to a logical “1” state.
Erase/Write Enable and Disable
The CAT93C86 powers up in the write disable state. Any
writing after power ? up or after an EWDS (write disable)
instruction must first be preceded by the EWEN (write
enable) instruction. Once the write instruction is enabled, it
will remain enabled until power to the device is removed, or
the EWDS instruction is sent. The EWDS instruction can be
used to disable all CAT93C86 write and clear instructions,
and will prevent any accidental writing or clearing of the
device. Data can be read normally from the device
regardless of the write enable/disable status.
SK
Erase All
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of t CSMIN . The falling
edge of CS will start the self clocking clear cycle of all
memory locations in the device. The clocking of the SK pin
is not necessary after the device has entered the self clocking
mode. The ready/busy status of the CAT93C86 can be
determined by selecting the device and polling the DO pin.
Once cleared, the contents of all memory bits return to a
logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t CSMIN . The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C86 can be determined by selecting the device and
polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
CS
A N
A N ? 1
A 0
t CS
STATUS
VERIFY
STANDBY
DI
1
1
1
DO
HIGH ? Z
t SV
BUSY
READY
t HZ
HIGH ? Z
t EW
Figure 5. Erase Instruction Timing
http://onsemi.com
6
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CAT93C86VIG-T3 | 制造商:ON Semiconductor 功能描述:EEPROM Serial-Microwire 16K-bit 2K x 8/1K x 16 2.5V/3.3V/5V 8-Pin SOIC N T/R |
| CAT93C86VI-GT3 | 制造商:ON Semiconductor 功能描述:IC EEPROM 16KBIT SERIAL 3MHZ SOIC-8 |
| CAT93C86VI-GT3-CUT TAPE | 制造商:ON 功能描述:CAT93C Series 16 kb (1kX16) 3 MHz 1.8 to 5.5 V Microwire Serial EEPROM - SOIC-8 |
| CAT93C86VI-TE13 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Catalyst Semiconductor 功能描述: |
| CAT93C86V-TE13 | 功能描述:电可擦除可编程只读存储器 (2048x8)(1024x16)16K RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
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