参数资料
| 型号： | CDB5467U |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 8/46页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR CS5467 ADC |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | CS5467 |
| 主要属性： | 电能表 |
| 次要属性： | 图形用户接口，SPI? 和 USB 接口 |
| 已供物品： | 板，线缆，软件 |
| 产品目录页面： | 754 (CN2011-ZH PDF) |
| 相关产品： | CS5467-ISZR-ND - IC ENERGY METERING 1PHASE 28SSOP 598-1197-5-ND - IC ENERGY METERING 1PHASE 28SSOP |
| 其它名称： | 598-1555 CDB-5467U |
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CS5467
ANALOG CHARACTERISTICS (Continued)
Parameter
Symbol
Min
Typ
Max
Unit
Analog Inputs (Voltage Inputs)
Differential Input Range
[(VIN+) – (VIN-)]
VIN
-
500
-
mV P-P
Total Harmonic Distortion
Crosstalk from Current inputs at Full Scale
(50, 60 Hz)
THD
65
-
75
-70
-
-
dB
dB
Input Capacitance
Effective Input Impedance
Noise (Referred to Input)
Offset Drift (Without the High-pass Filter)
Gain Error
All Gain Ranges
IC
EII
N V
OD
GE
-
2
-
-
-
2.0
-
-
16.0
±3.0
-
-
140
-
pF
M ?
μV rms
μV/°C
%
Temperature
Temperature Accuracy
T
-
±5
-
°C
Power Supplies
Power Supply Currents (Active State)
I A+
PSCA
-
1.5
-
mA
I D+ (VA+ = VD+ = 5 V)
I D+ (VA+ = 5 V, VD+ = 3.3 V)
PSCD
PSCD
-
-
3.5
2.3
-
-
mA
mA
Power Consumption
Active State (VA+ = VD+ = 5 V)
-
25
33
mW
Active State (VA+ = 5 V, VD+ = 3.3 V)
Stand-by State
Sleep State
PC
-
-
-
15
7
10
20
-
-
mW
mW
uW
Power Supply Rejection Ratio (50, 60 Hz)
Voltage
Current (Gain = 50x)
Current (Gain = 10x)
PSRR
48
68
60
55
75
65
-
-
-
dB
dB
dB
PFMON Low-voltage Trigger Threshold
PFMON High-voltage Power-on Trip Point
PMLO
PMHI
2.3
-
2.45
2.55
-
2.7
V
V
PSRR = 20 ? log ----------
Notes: 3. Applies before system calibration.
4. All outputs unloaded. All inputs CMOS level.
5. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV
(zero-to-peak) (60 Hz) sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The
“+” and “-” input pins of both input channels are shorted to AGND. The CS5467 is then commanded to
continuous conversion acquisition mode, and digital output data is collected for the channel under test.
The (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted
into the (zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be applied
at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined
as Veq. PSRR is (in dB) :
150
V eq
6. When the voltage level on PFMON is sagging and LSD bit = 0, this is the voltage at which LSD is set to 1.
7. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on
PFMON at which the LSD bit can be permanently reset back to 0.
8
DS714F3
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