CDB8420 (Cirrus) PDF资料下载 Datasheet(11/94 页)

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参数资料

型号：	CDB8420
厂商：	Cirrus Logic Inc
文件页数：	11/94页
文件大小：	0K
描述：	EVALUATION BOARD FOR CS8420
标准包装：	1
主要目的：	音频，采样率转换器
嵌入式：	是，MCU，8 位
已用 IC / 零件：	CS8420
主要属性：	带数字音频发射器和接收器的采样率转换器
次要属性：	44.1、48、96 kHz 输出采样率，AES/EBU，S/PDIF，EIAJ-340，GUI
已供物品：	板
相关产品：	598-1125-5-ND - IC SAMPLE RATE CONVERTER 28SOIC
其它名称：	598-1782

DS245F4

CS8420

THREE-WIRE SERIAL AUDIO PORTS

A 3-wire serial audio input port and a 3-wire serial audio output port is provided. Each port can be adjusted to suit

the attached device via control registers. The following parameters are adjustable: master or slave, serial clock fre-

quency, audio data resolution, left or right justification of the data relative to left/right clock, optional 1-bit cell delay

of the 1st data bit, the polarity of the bit clock and the polarity of the left/right clock. By setting the appropriate control

bits, many formats are possible.

Figure 17 shows a selection of common input formats, along with the control bit settings. The clocking of the input

section of the CS8420 may be derived from the incoming ILRCK word rate clock, using the on-chip PLL. The PLL

operation is described in the AES receiver description on page 22. In the case of use with the serial audio input port,

the PLL locks onto the leading edges of the ILRCK clock.

Figure 18 shows a selection of common output formats, along with the control bit settings. A special AES3 direct

output format is included, which allows serial output port access to the V, U, and C bits embedded in the serial audio

data stream. The P bit is replaced by a bit indicating the location of the start of a block. This format is only available

when the serial audio output port is being clocked by the AES3 receiver-recovered clock. Also, the received-channel

status block start signal is only available in Hardware mode 5, as the RCBL pin.

In Master mode, the left/right clock and the serial bit clock are outputs, derived from the appropriate clock domain

master clock.

In Slave mode, the left/right clock and the serial bit clock are inputs. The left/right clock must be synchronous to the

appropriate master clock, but the serial bit clock can be asynchronous and discontinuous if required. By appropriate

phasing of the left/right clock and control of the serial clocks, multiple CS8420’s can share one serial port. The

left/right clock should be continuous, but the duty cycle does not have to be 50%, provided that enough serial clocks

are present in each phase to clock all the data bits. When in Slave mode, the serial audio output port must be set to

left-justified or IS data.

When using the serial audio output port in Slave mode with an OLRCK input which is asynchronous to the port’s

data source, then an interrupt bit is provided to indicate when repeated or dropped samples occur.

The CS8420 allows immediate mute of the serial audio output port audio data via a control register bit.

相关代理商/技术参数	参数描述
CDB8421	功能描述:音频 IC 开发工具 2-Ch 32-Bit 192kHz sample rate converte RoHS:否制造商:Texas Instruments 产品:Evaluation Kits 类型:Audio Amplifiers 工具用于评估:TAS5614L 工作电源电压:12 V to 38 V
CDB8422	功能描述:界面开发工具 Eval Bd 192kHz SRC S/PDIF Receiver RoHS:否制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V
CDB8427	功能描述:音频 IC 开发工具 Eval Bd 96kHz Dig. Audio Transcvr RoHS:否制造商:Texas Instruments 产品:Evaluation Kits 类型:Audio Amplifiers 工具用于评估:TAS5614L 工作电源电压:12 V to 38 V
CDB8952	制造商:Cirrus Logic 功能描述:NOT RECOMMENDED FOR NEW DESIGNS - USE CDB8952T - Bulk 制造商:Cirrus Logic 功能描述:Tools Development kit Kit Con
CDB8952T	功能描述:以太网开发工具 Eval Bd 100BASE-TX/ 10BASE-T Transceiver RoHS:否制造商:Micrel 产品:Evaluation Boards 类型:Ethernet Transceivers 工具用于评估:KSZ8873RLL 接口类型:RMII 工作电源电压:

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