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参数资料
| 型号： | CDB8420 |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 52/94页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR CS8420 |
| 标准包装： | 1 |
| 主要目的： | 音频，采样率转换器 |
| 嵌入式： | 是，MCU，8 位 |
| 已用 IC / 零件： | CS8420 |
| 主要属性： | 带数字音频发射器和接收器的采样率转换器 |
| 次要属性： | 44.1、48、96 kHz 输出采样率，AES/EBU，S/PDIF，EIAJ-340，GUI |
| 已供物品： | 板 |
| 相关产品： | 598-1125-5-ND - IC SAMPLE RATE CONVERTER 28SOIC |
| 其它名称： | 598-1782 |
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56
DS245F4
CS8420
13.2
Hardware Mode 1 Description (DEFAULT Data Flow, AES3 Input)
Hardware Mode 1 data flow is shown in Figure 24. Audio data is input via the AES3 receiver, and rate con-
verted. The audio data at the new rate is then output both via the serial audio output port and via the AES3
transmitter.
The channel status data, user data and validity bit information are handled in four alternative modes: 1A and
1B, determined by a start-up resistor on the COPY pin. In mode 1A, the received PRO, COPY, ORIG, EM-
PH, and AUDIO channel status bits are output on pins. The transmitted channel status bits are copied from
the received channel status data, and the transmitted U and V bits are 0.
In mode 1B, only the COPY and ORIG pins are output, and reflect the received channel status data. The
transmitted channel status bits, user data and validity bits are input serially via the PRO/C, EMPH/U and
AUDIO/V pins. Figure 20 shows the timing requirements.
Start-up options are shown in Table 8, and allow choice of the serial audio output port as a master or slave,
choice of four serial audio output port formats, and the source for transmitted C, U and V data. The following
pages contain the detailed pin descriptions for Hardware mode 1.
If a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample will be held.
SDOUT
RMCK
RERR
COPY
Function
LO
-
Serial Output Port is Slave
HI
-
Serial Output Port is Master
-
LO
Mode1A: C transmitted data is copied from received data, U & V = 0,
received PRO, EMPH, AUDIO are visible.
-
HI
Mode 1B: CUV transmitted data is input serially on pins, received PRO,
EMPH, AUDIO are not visible
-
LO
Serial Output Format OF1
-
LO
HI
Serial Output Format OF2
-
HI
LO
Serial Output Format OF3
-
HI
Serial Output Format OF4
Table 8. Hardware Mode 1 Start-Up Options
AES3
Encoder
&Tx
Serial
Audio
Output
AES3 Rx
&
Decoder
Sample
Rate
Converter
C&Ubit Data Buffer
Clocked by
Output Clock
Clocked by
Input Derived Clock
RXP
RXN
OLRCK
OSCLK
SDOUT
TXP
TXN
RMCK
RERR
COPY ORIG EMPH/U
TCBLD
PRO/C
AUDIO/V
TCBL
MUTE
DFC0
DFC1
S/AES
VD+
H/S
Output
Clock
Source
OMCK
Power supply pins (VD+, VA+, DGND, AGND), the reset pin (RST) and the PLL filter pin (FILT)
are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
Figure 24. Hardware Mode 1 - Default Data Flow, AES3 Input
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CDB8421 | 功能描述:音频 IC 开发工具 2-Ch 32-Bit 192kHz sample rate converte RoHS:否 制造商:Texas Instruments 产品:Evaluation Kits 类型:Audio Amplifiers 工具用于评估:TAS5614L 工作电源电压:12 V to 38 V |
| CDB8422 | 功能描述:界面开发工具 Eval Bd 192kHz SRC S/PDIF Receiver RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
| CDB8427 | 功能描述:音频 IC 开发工具 Eval Bd 96kHz Dig. Audio Transcvr RoHS:否 制造商:Texas Instruments 产品:Evaluation Kits 类型:Audio Amplifiers 工具用于评估:TAS5614L 工作电源电压:12 V to 38 V |
| CDB8952 | 制造商:Cirrus Logic 功能描述:NOT RECOMMENDED FOR NEW DESIGNS - USE CDB8952T - Bulk 制造商:Cirrus Logic 功能描述:Tools Development kit Kit Con |
| CDB8952T | 功能描述:以太网开发工具 Eval Bd 100BASE-TX/ 10BASE-T Transceiver RoHS:否 制造商:Micrel 产品:Evaluation Boards 类型:Ethernet Transceivers 工具用于评估:KSZ8873RLL 接口类型:RMII 工作电源电压: |
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