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参数资料
| 型号： | CM1231-02SO |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/12页 |
| 文件大小： | 0K |
| 描述： | DIODE ESD CLAMP 2CH SOT23-6 |
| 标准包装： | 3,000 |
| 电极标记： | 2 通道阵列 - 双向 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-6 |
| 供应商设备封装： | SOT-23-6 |
| 包装： | 带卷 (TR) |
| 其它名称： | CM1231-02SO-ND CM1231-02SOOSTR |
CM1231 ? 02SO
APPLICATION INFORMATION
CM1231 ? 02SO Application and Guidelines
The CM1231 ? 02SO has an integrated zener diode
between V P and V N (for each of the two stages). This greatly
reduces the effect of supply rail inductance L 2 on V CL by
clamping V P at the breakdown voltage of the zener diode.
However, for the lowest possible V CL , especially when V P
is biased at a voltage significantly below the zener
breakdown voltage, it is recommended that a 0.22 m F
ceramic chip capacitor be connected between V P and the
ground plane.
With the CM1231 ? 02SO, this additional bypass capacitor
is generally not required.
As a general rule, the ESD Protection Array should be
located as close as possible to the point of entry of expected
electrostatic discharges. The power supply bypass capacitor
mentioned above should be as close to the V P pin of the
Protection Array as possible, with minimum PCB trace
lengths to the power supply, ground planes and between the
signal input and the ESD device to minimize stray series
inductance.
Figure 14. Typical Layout with Optional V P Cap Footprint
Additional Information
See also ON Semiconductor Application Note, “Design Considerations for ESD Protection,” in the Applications section.
http://onsemi.com
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