参数资料
| 型号： | COP8CCR9LVA8 |
| 厂商： | National Semiconductor |
| 文件页数： | 60/111页 |
| 文件大小： | 0K |
| 描述： | IC MCU EEPROM 8BIT 68-PLCC |
| 标准包装： | 18 |
| 系列： | COP8™ 8C |
| 核心处理器： | COP8 |
| 芯体尺寸： | 8-位 |
| 速度： | 20MHz |
| 连通性： | Microwire/Plus（SPI），UART/USART |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 59 |
| 程序存储器容量： | 32KB（32K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 数据转换器： | A/D 16x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 68-LCC（J 形引线） |
| 包装： | 管件 |
| 其它名称： | *COP8CCR9LVA8 |
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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
Figure 5-14. Wake-up from HALT
5.12.3.2 High Speed Idle Mode
In the IDLE mode, program execution stops and power consumption is reduced to a very low level as with
the HALT mode. However, the high speed oscillator, IDLE Timer (Timer T0), and Clock Monitor continue
to operate, allowing real time to be maintained. The device remains idle for a selected amount of time up
to 65,536 instruction cycles, or 32.768 milliseconds with a 2 MHz instruction clock frequency, and then
automatically exits the IDLE mode and returns to normal program execution.
The device is placed in the IDLE mode under software control by setting the IDLE bit (bit 6 of the Port G
data register).
The IDLE Timer window is selectable from one of five values, 4k, 8k, 16k, 32k or 64k instruction cycles.
Selection of this value is made through the ITMR register.
The IDLE mode uses the on-chip IDLE Timer (Timer T0) to keep track of elapsed time in the IDLE state.
The IDLE Timer runs continuously at the instruction clock rate, whether or not the device is in the IDLE
mode. Each time the bit of the timer associated with the selected window toggles, the T0PND bit is set, an
interrupt is generated (if enabled), and the device exits the IDLE mode if in that mode. If the IDLE Timer
interrupt is enabled, the interrupt is serviced before execution of the main program resumes. (However,
the instruction which was started as the part entered the IDLE mode is completed before the interrupt is
serviced. This instruction should be a NOP which should follow the enter IDLE instruction.) The user must
reset the IDLE Timer pending flag (T0PND) before entering the IDLE mode.
As with the HALT mode, this device can also be returned to normal operation with a reset, or with a Multi-
Input Wake-up input. Upon reset the ITMR register is cleared and the ITMR register selects the 4,096
instruction cycle tap of the Idle Timer.
The IDLE Timer cannot be started or stopped under software control, and it is not memory mapped, so it
cannot be read or written by the software. Its state upon Reset is unknown. Therefore, if the device is put
into the IDLE mode at an arbitrary time, it will stay in the IDLE mode for somewhere between 1 and the
selected number of instruction cycles.
In order to precisely time the duration of the IDLE state, entry into the IDLE mode must be synchronized to
the state of the IDLE Timer. The best way to do this is to use the IDLE Timer interrupt, which occurs on
every underflow of the bit of the IDLE Timer which is associated with the selected window. Another
method is to poll the state of the IDLE Timer pending bit T0PND, which is set on the same occurrence.
The Idle Timer interrupt is enabled by setting bit T0EN in the ICNTRL register.
Any time the IDLE Timer window length is changed there is the possibility of generating a spurious IDLE
Timer interrupt by setting the T0PND bit. The user is advised to disable IDLE Timer interrupts prior to
changing the value of the ITSEL bits of the ITMR Register and then clear the TOPND bit before
attempting to synchronize operation to the IDLE Timer.
52
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
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