参数资料
型号: COREPCIF-RM
厂商: Microsemi SoC
文件页数: 61/156页
文件大小: 0K
描述: IP MODULE COREPCIF
标准包装: 1
系列: *
Burst Transfer with a Slow Backend
During write transfers, the backend asserts its WR_BE_RDY signal when it is ready. This causes the core to assert
TRDYN and then, assuming that IRDYN was active on the PCI bus, causes WR_BE_NOW to be asserted on the
following clock edge. This allows the backend to control the transfer rate.
cycle
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
clk
framen
ad[31:0]
ADDR
0
1
2
3
cben[3:0]
par
devseln
irdyn
trdyn
dp_start
dp_done
bar_select[2:0]
wr_cyc
wr_be_rdy
7
0
0
wr_be_now[3:0]
F
0
F
0
F
0
F
mem_add[15:0]
mem_data_out[31:0]
0000
0
0004
1
0008
2
000C
3
Figure 6-12 · Backend Burst Write Cycle with Slow Backend
v4.0
61
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相关代理商/技术参数
参数描述
COREPCIF-RMFL 功能描述:IP MODULE 制造商:microsemi corporation 系列:- 零件状态:在售 类型:许可证 应用:- 版本:- 许可长度:- 许可 - 用户明细:- 操作系统:- 配套使用产品/相关产品:Microsemi 器件 媒体分发类型:- 标准包装:1
COREPCIF-UR 功能描述:HW/SW/OTHER 制造商:microsemi corporation 系列:* 零件状态:在售 标准包装:1
COREPCI-SN 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPCI-SR 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41
COREPCI-UR 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:CorePCI v5.41