参数资料
型号: COREPCIF-RM
厂商: Microsemi SoC
文件页数: 85/156页
文件大小: 0K
描述: IP MODULE COREPCIF
标准包装: 1
系列: *
Simple DMA Transfer
cycle
A0
A1
A2
A3
0
1
2
3
4
5
6
7
8
9
clk
idsel
framen
cben[3:0]
6
0
ad[31:0]
ADDR
0
1
2
3
par
devseln
irdyn
trdyn
reqn
gntn
mast_active
dp_start
dp_done
dma_bar[2:0]
wr_cyc
wr_be_rdy
wr_be_now[3:0]
F
mem_add[11:0]
000
004
008 00C
mem_data_out[31:0]
0
1
2
3
Figure 6-36 · DMA Burst Write Cycle
During the DMA burst write cycles, it is normal for an additional write cycle, such as cycle nine in Figure 6-36 , to take
place one clock cycle after MAST_ACTIVE has been deasserted. If necessary, MAST_ACTIVE can be delayed by a
clock cycle externally to generate a version that will still be active when the last write occurs.
v4.0
85
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相关代理商/技术参数
参数描述
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