参数资料
| 型号： | CS1601-FSZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 10/16页 |
| 文件大小： | 0K |
| 描述： | IC PFC CONTROLLER BALLAST 8SOIC |
| 产品变化通告： | CS1501, 1601 Datasheet Update Change 11/Jan/2012 |
| 设计资源： | CS150x/160x PCB Layout Guidelines Driving Mosfets with CS1501/1601 CS1501/1601 Driving ZCD Pin from Mosfet Drain |
| 特色产品： | CS1501/CS1601 Power Factor Correction IC Controllers |
| 标准包装： | 100 |
| 类型： | PFC/镇流器控制器 |
| 频率： | 70kHz |
| 电流 - 电源： | 1.5mA |
| 电流 - 输出： | 1A |
| 电源电压： | 7.9 V ~ 17 V |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 散装 |
| 其它名称： | 598-1915 |
CS1601
5.2 Startup vs. Normal Operation Mode
The CS1601 has two discrete operation modes: startup and
5.4 Output Power and PFC Boost Inductor
In normal operating mode, the nominal output power is
2 V link – ? V in ? min ? ? 2 ?
2 ? f max ? L B ? V link
normal. Startup mode will be activated when V link is less than
90% of nominal value, V O(startup) , and remains active until V link
Startup mode is activated during initial system power-up. Any
estimated by the following equation:
P o = ? ? ? ? ? V in ? min ? ? ? ---------------------------------------------------------
[Eq.1]
V link drop to less than V O(startup) , such as a load change, can
cause the system to enter startup mode until V link is brought
back into regulation.
V link
[V]
where:
P o
?
rated output power of the system
efficiency of the boost converter (estimated as 100%
by the PFC algorithm)
100%
90%
V in(min) minimum RMS line voltage measured after the
rectifier and EMI filter. V in(min) is equal to 90Vrms or
108 Vrms depending on the AC Line Voltage
Normal
Mode
Normal
Mode
V link
operating range.
nominal PFC output voltage; V link = 400V when
V i n ( m i n ) = 9 0 Vr m s o r V l i n k = 4 6 0 V w h e n
V in(min) = 108Vrms
t [ms]
Figure 14. Startup and Normal Modes
f max
L B
maximum switching frequency; for the CS1601
f max = 70kHz and the CS1601H f max = 100kHz
boost inductor specified by rated power requirement
Startup mode is defined as a surge of current delivering
maximum power to the output regardless of the load. During
every active switch cycle, the 'ON' time is calculated to drive a
constant peak current over the entire line cycle. However, the
'OFF' time is calculated based on the DCM/CCM boundary
equation.
??? margin factor to guarantee rated output power (P o )
against boost inductor tolerances.
Equation 1 is provided for explanation purposes only. Using
substituted required design values for V link and f max gives the
following equation:
P o = ? ? ? ? ? 108V ? ? -------------------------------------------------------------
5.3 Burst Mode
Burst mode is used to improve system efficiency when the
2 460V – ? 108V ? 2 ?
2 ? 70kHz ? L B ? 460V
[Eq.2]
system output power (P o ) is <5% of nominal. Burst mode is
implemented by intermittently disabling the PFC over a full
half-line period under light-load conditions, as shown in
Changing the value for the V link voltage is not recommended.
Solving Equation 2 for the PFC boost inductor L B gives the
following equation:
L B = ? ? ? ? ? 108V ? ? -------------------------------------------------------------
P o
[W]
2 460V – ? 108V ? 2 ?
2 ? 70kHz ? P o ? 460V
[Eq.3]
Burst Threshold
If a value of the boost inductor other than that obtained from
V in
[V]
V in
Burst Mode
Active
PFC
Disable
t [ms]
FET
V gs
Equation 3 above is used, the total output power capability
and the minimum input voltage threshold will differ according
to Equation 2. Note that if the input voltage drops below
108Vrms and the inductance value is <L B , the link voltage
V link will drop below 460V and fall out of regulation.
L < L B ? ?
L = L B
Figure 15. Burst Mode
t [ms]
L > L B ? ?
108
V AC(rms)
305
Figure 16. Relative Effects of Varying Boost Inductance
10
DS931F3
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