参数资料
| 型号： | CS1601-FSZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 11/16页 |
| 文件大小： | 0K |
| 描述： | IC PFC CONTROLLER BALLAST 8SOIC |
| 产品变化通告： | CS1501, 1601 Datasheet Update Change 11/Jan/2012 |
| 设计资源： | CS150x/160x PCB Layout Guidelines Driving Mosfets with CS1501/1601 CS1501/1601 Driving ZCD Pin from Mosfet Drain |
| 特色产品： | CS1501/CS1601 Power Factor Correction IC Controllers |
| 标准包装： | 100 |
| 类型： | PFC/镇流器控制器 |
| 频率： | 70kHz |
| 电流 - 电源： | 1.5mA |
| 电流 - 输出： | 1A |
| 电源电压： | 7.9 V ~ 17 V |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 散装 |
| 其它名称： | 598-1915 |
CS1601
5.5 PFC Output Capacitor
The value of the PFC output capacitor needs to be selected
based upon voltage ripple and hold-up requirements. To
ensure system stability with the digital controller, the
recommended value of the capacitor is within the range of
0.25 ? F/watt to 0.5 ? F/watt with a V link voltage of 460V.
5.7 Valley Switching
The zero-current detection (ZCD) pin is monitored for
demagnetization in the auxiliary winding of the boost inductor
(L B ). The ZCD circuit is designed to detect the V Aux
valley/zero crossings by sensing the voltage transformed onto
the auxiliary winding of L B .
5.6 Output IFB Sense and Input IAC Sense
A current proportional to the PFC output voltage, V link , is
supplied to the IC on pin IFB and is used as a feedback control
signal. This current is compared against an internal fixed-
L B
N:1
D2
V link
FE T Drain
value reference current.
-
The ADC is used to measure the magnitude of the I IFB current
through resistor R IFB . The magnitude of the I IFB current is then
compared to an internal reference current of (I ref ) 129 ? A.
V link
I Aux
+
R3
I Z CD
ZCD
5
CS1601
+
V th( Z CD)
ZCD_below_zero
V Aux
R4
C p
I FB
R5
R6
R IFB
IFB
1
8
V DD
15 k
24 k
CS1601
ADC
Demag
Comparator
-
Figure 19. ZCD Input Pin Model
The objective of zero-voltage switching is to initiate each
MOSFET switching cycle when its drain-source voltage is at
the lowest possible voltage potential, thus reducing switching
losses. The CS1601 uses an auxiliary winding on the PFC
R IFB = ----------------------------- = -------------------------------
Figure 17. IFB Input Pin Model
Resistor R IFB sets the feedback current and is calculated as
follows:
V link – V DD 460V – V DD
I ref 129 ? A [Eq.4]
By using digital loop compensation, the voltage feedback
signal does not require an external compensation network.
A current proportional to the AC input voltage is supplied to the
IC on pin IAC and is used by the PFC control algorithm.
V rec t
boost inductor to implement zero-voltage switching.
Zero Crossing
Detection
ZCD
GD ‘ON’
ZCD_below _zero
Figure 20. Zero-voltage Switch
During each switching cycle, when the boost diode current
I AC
R1
R2
R IAC
IA C
3
8
V DD
15 k
24 k
CS1601
ADC
reaches zero, the boost MOSFET drain-source voltage begins
oscillating at the resonant frequency of the boost inductor and
MOSFET parasitic output capacitance. The ZCD_below_zero
signal transitions from high to low just prior to a local minimum
of the MOSFET drain-source voltage oscillation. The zero-
crossing detect circuit ensures that a ZCD_below_zero pulse
will only be generated when the comparator output is
continuously high for a nominal time period (t ZCB ) of 200ns.
Therefore, any negative edges on the comparator's output
Figure 18. IAC Input Pin Model
Resistor R IAC sets the IAC current and is derived as follows:
due to spurious glitches will not cause a pulse to be
generated.
Due to the CS1601's variable-frequency control, the MOSFET
R IAC = R IFB
[Eq.5]
switching cycle will not always be initiated at the first resonant
valley. The external circuitry should be designed so that the
For optimal performance, resistors R IAC and R IFB should use
1% tolerance or better resistors for best V link voltage accuracy.
DS931F3
current (I ZCD ) at the ZCD pin is approximately ±1.0mA. The
11
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