参数资料
型号: CS4333-KSR
厂商: CRYSTAL SEMICONDUCTOR CORP
元件分类: DAC
中文描述: SERIAL INPUT LOADING, 18-BIT DAC, PDSO8
封装: PLASTIC, SOIC-8
文件页数: 10/29页
文件大小: 1076K
代理商: CS4333-KSR
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
DS752PP10
18
5.15 Switching Characteristics — Parallel Control Port - Motorola Slave Mode
Parameter
Symbo
lMin
Typical
Max
Unit
Address setup before PCP_CS and PCP_DS low
tmas
5—
ns
Address hold time after PCP_CS and PCP_DS low
tmah
5—
ns
Read
Delay between PCP_DS then PCP_CS low or PCP_CS then
PCP_DS low
tmcdr
0—
ns
Data valid after PCP_CS and PCP_DS low with PCP_R/W high
tmdd
19
ns
PCP_CS and PCP_DS low for read
tmrpw
24
ns
Data hold time after PCP_CS or PCP_DS high after read
tmdhr
8—
ns
Data high-Z after PCP_CS or PCP_DS high after read
tmdis
18
ns
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next
read1
1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware
application. Hardware handshaking on the PCP_
BSY pin/bit should be observed to prevent overflowing the input data buffer.
CS4953x4/CS4970x4 System Designer’s Guide should be consulted for the firmware speed limitations.
tmrd
30
ns
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next
write1
tmrdtw
30
ns
PCP_RW rising to PCP_IRQ falling
tmrwirqh
12
ns
Write
Delay between PCP_DS then PCP_CS low or PCP_CS then
PCP_DS low
tmcdw
0—
ns
Data setup before PCP_CS or PCP_DS high
tmdsu
8—
ns
PCP_CS and PCP_DS low for write
tmwpw
24
ns
PCP_R/W setup before PCP_CS AND PCP_DS low
tmrwsu
24
ns
PCP_R/W hold time after PCP_CS or PCP_DS high
tmrwhld
8—
ns
Data hold after PCP_CS or PCP_DS high
tmdhw
8—
ns
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low with
PCP_R/W high for next read1
tmwtrd
30
ns
PCP_CS or PCP_DS high to PCP_CS and PCP_DS low for next
write1
tmwd
30
ns
PCP_RW rising to PCP_BSY falling
tmrwbsyl
—2*DCLKP + 20
ns
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