参数资料
型号: CS4333-KSR
厂商: CRYSTAL SEMICONDUCTOR CORP
元件分类: DAC
中文描述: SERIAL INPUT LOADING, 18-BIT DAC, PDSO8
封装: PLASTIC, SOIC-8
文件页数: 6/29页
文件大小: 1076K
代理商: CS4333-KSR
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
DS752PP10
14
.
Figure 4. Serial Control Port - SPI Master Mode Timing
5.12 Switching Characteristics — Serial Control Port - I2C Slave Mode
Parameter
Symbol
Min
Typical
Max
Units
SCP_CLK frequency1
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_
BSY pin
should be implemented to prevent overflow of the input data buffer.
fiicck
——
400
kHz
SCP_CLK low time
tiicckl
1.25
s
SCP_CLK high time
tiicckh
1.25
s
SCP_SCK rising to SCP_SDA rising or falling for START or
STOP condition
tiicckcmd
1.25
s
START condition to SCP_CLK falling
tiicstscl
1.25
s
SCP_CLK falling to STOP condition
tiicstp
2.5
s
Bus free time between STOP and START conditions
tiicbft
3—
s
Setup time SCP_SDA input valid to SCP_CLK rising
tiicsu
100
ns
Hold time SCP_SDA input after SCP_CLK falling
tiich
20
ns
SCP_CLK low to SCP_SDA out valid
tiicdov
——
18
ns
SCP_CLK falling to SCP_IRQ rising
tiicirqh
——
3*DCLKP + 40
ns
NAK condition to SCP_IRQ low
tiicirql
—3*DCLKP + 20
ns
SCP_CLK rising to SCB_BSY low
tiicbsyl
—3*DCLKP + 20
ns
EE_CS#
SCP_CLK
SCP_MISO
SCP_MOSI
0
12
67
0
56
7
tspicss
tspickl
tspickh
tspidsu
tspidh
tspidov
A6
A5
A0
R/W
MSB
LSB
MSB
LSB
tspicsh
tspicsx
fspisck
tspidz
tspicsl
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