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参数资料
型号： CS4398-CZZ
厂商： Cirrus Logic Inc
文件页数： 15/46页
文件大小： 0K
描述： IC DAC 120DB 192KHZ W/VC 28TSSOP
标准包装： 50
位数： 24
数据接口： 串行
转换器数目： 2
电压电源： 模拟和数字
功率耗散（最大）： 340mW
工作温度： -10°C ~ 70°C
安装类型： 表面贴装
封装/外壳： 28-TSSOP（0.173"，4.40mm 宽）
供应商设备封装： 28-TSSOP
包装： 管件
输出数目和类型： 4 电压，单极
采样率（每秒）： 216k
产品目录页面： 757 (CN2011-ZH PDF)
配用： 598-1155-ND - BOARD EVAL FOR CS4398 DAC
其它名称： 598-1067-5
22
DS568F1
CS4398
Table 2. Common Clock Frequencies
4.6
Stand-alone Mode Settings
In Stand-Alone mode (also referred to as “Hardware mode”) the device is configured using the M0 through
M3 pins. These pins must be connected to either the VLC supply or ground. The Interface format is set by
pins M0 and M1. The sample rate range/oversampling mode (Single/Double/Quad-Speed mode) and de-
emphasis are set by pins M2 and M3. The settings can be found in Tables 3 and 4.
Table 3. Digital Interface Format, Stand-Alone Mode Options
Table 4. Mode Selection, Stand-Alone Mode Options
The following features are always enabled in Stand-Alone mode: Auto-mute on zero data, Auto MUTEC po-
larity detect, ramp volume from mute to 0dB by 1/8th dB steps every LRCK (soft ramp) after reset or clock
mode change, and the fast roll-off interpolation filter is used.
The following features are not available in Stand-Alone mode: DSD mode, Right-Justified 20- and 18-bit se-
rial audio interfaces, MCLK divide-by-2 and MCLK divide-by-3 (allows 1024 and 1152 clock ratios), slow roll-
off interpolation filter, volume control, ATAPI mixing, 48 kHz and 32 kHz de-emphasis, and all other features
enabled by registers that are not mentioned above.
Mode
(sample-
rate range)
Sample
Rate
(kHz)
MCLK (MHz)
MCLKDIV2
MCLKDIV3
MCLK Ratio
256x
384x
512x
768x
1024x
1152x
Single-Speed
(32to50kHz)
32
8.1920
12.2880
16.3840
24.5760
32.7680
36.8640
44.1
11.2896
16.9344
22.5792
33.8688
45.1584
-
48
12.2880
18.4320
24.5760
36.8640
49.1520
-
MCLK Ratio
128x
192x
256x
384x
512x
-
Double-Speed
(50 to 100 kHz)
64
8.1920
12.2880
16.3840
24.5760
32.7680
-
88.2
11.2896
16.9344
22.5792
33.8688
45.1584
-
96
12.2880
18.4320
24.5760
36.8640
49.1520
-
MCLK Ratio
64x*
96x
128x
192x
256x
-
Quad-Speed
(100 to 200 kHz)
176.4
11.2896*
16.9344
22.5792
33.8688
45.1584
-
192
12.2880*
18.4320
24.5760
36.8640
49.1520
-
These modes are only available in Control Port mode by setting the appropriate MCLKDIV bit.
* This MCLK ratio limits the audio word length to 16 bits; see Table 1 on page 21
M1
M0
Description
Format
Figure
00
Left-Justified, up to 24-bit data
03
01
IS, up to 24-bit data
14
10
Right-Justified, 16-bit Data
25
11
Right-Justified, 24-bit Data
35
M3
M2
Description
00
Single-Speed without De-Emphasis (32 to 50 kHz sample rates)
01
Single-Speed with 44.1 kHz De-Emphasis; see Figure 17 on page 30
10
Double-Speed (50 to 100 kHz sample rates)
11
Quad-Speed (100 to 200 kHz sample rates)
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