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参数资料
型号： CS5346-DQZR
厂商： CIRRUS LOGIC INC
元件分类： ADC
中文描述： 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQFP48
封装： LEAD FREE, MS-022, LQFP-48
文件页数： 12/40页
文件大小： 402K
代理商： CS5346-DQZR
2
DS861PP2
CS5346
TABLE OF CONTENTS
1. PIN DESCRIPTIONS - CS5346 ............................................................................................................. 5
2. PIN COMPATIBILITY - CS5345/CS5346 DIFFERENCES ..................................................................... 7
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8
RECOMMENDED OPERATING CONDITIONS ................................................................................... 8
ABSOLUTE MAXIMUM RATINGS .......................................................................................................8
ANALOG CHARACTERISTICS (COMMERCIAL) ................................................................................ 9
ANALOG CHARACTERISTICS (COMMERCIAL) CONT. .................................................................. 10
ANALOG CHARACTERISTICS (AUTOMOTIVE) ............................................................................... 11
ANALOG CHARACTERISTICS (AUTOMOTIVE) CONT. ................................................................... 12
DIGITAL FILTER CHARACTERISTICS .............................................................................................. 13
DC ELECTRICAL CHARACTERISTICS ............................................................................................. 14
DIGITAL INTERFACE CHARACTERISTICS ...................................................................................... 15
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT ............................................................. 16
SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT ............................................ 18
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ........................................... 19
4. TYPICAL CONNECTION DIAGRAM ................................................................................................... 20
5. APPLICATIONS ................................................................................................................................... 21
5.1 Recommended Power-Up Sequence ............................................................................................. 21
5.2 System Clocking ............................................................................................................................. 21
5.2.1 Master Clock ......................................................................................................................... 21
5.2.2 Master Mode ......................................................................................................................... 22
5.2.3 Slave Mode ........................................................................................................................... 22
5.3 High-Pass Filter and DC Offset Calibration .................................................................................... 22
5.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................................23
5.5 Input Connections ........................................................................................................................... 23
5.5.1 Analog Input Configuration for 1 VRMS Input Levels ............................................................ 23
5.5.2 Analog Input Configuration for 2 VRMS Input Levels ............................................................ 24
5.6 PGA Auxiliary Analog Output ......................................................................................................... 25
5.7 Control Port Description and Timing ............................................................................................... 25
5.7.1 SPI Mode ............................................................................................................................... 25
5.7.2 IC Mode ................................................................................................................................ 26
5.8 Interrupts and Overflow .................................................................................................................. 27
5.9 Reset .............................................................................................................................................. 28
5.10 Synchronization of Multiple Devices ............................................................................................. 28
5.11 Grounding and Power Supply Decoupling .................................................................................... 28
6. REGISTER QUICK REFERENCE ........................................................................................................ 29
7. REGISTER DESCRIPTION .................................................................................................................. 30
7.1 Chip ID - Register 01h .................................................................................................................... 30
7.2 Power Control - Address 02h ......................................................................................................... 30
7.2.1 Freeze (Bit 7) ......................................................................................................................... 30
7.2.2 Power-Down MIC (Bit 3) ........................................................................................................ 30
7.2.3 Power-Down ADC (Bit 2) ....................................................................................................... 30
7.2.4 Power-Down Device (Bit 0) ................................................................................................... 30
7.3 ADC Control - Address 04h ............................................................................................................ 31
7.3.1 Functional Mode (Bits 7:6) .................................................................................................... 31
7.3.2 Digital Interface Format (Bit 4) .............................................................................................. 31
7.3.3 Mute (Bit 2) ............................................................................................................................ 31
7.3.4 High-Pass Filter Freeze (Bit 1) .............................................................................................. 31
7.3.5 Master / Slave Mode (Bit 0) ................................................................................................... 31
7.4 MCLK Frequency - Address 05h .................................................................................................... 32
7.4.1 Master Clock Dividers (Bits 6:4) ............................................................................................ 32
7.5 PGAOut Control - Address 06h ...................................................................................................... 32
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