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参数资料
型号： CS5346-DQZR
厂商： CIRRUS LOGIC INC
元件分类： ADC
中文描述： 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PQFP48
封装： LEAD FREE, MS-022, LQFP-48
文件页数： 23/40页
文件大小： 402K
代理商： CS5346-DQZR
DS861PP2
3
CS5346
7.5.1 PGAOut Source Select (Bit 6) ............................................................................................... 32
7.6 Channel B PGA Control - Address 07h .......................................................................................... 32
7.6.1 Channel B PGA Gain (Bits 5:0) ............................................................................................. 32
7.7 Channel A PGA Control - Address 08h .......................................................................................... 33
7.7.1 Channel A PGA Gain (Bits 5:0) ............................................................................................. 33
7.8 ADC Input Control - Address 09h ................................................................................................... 33
7.8.1 PGA Soft Ramp or Zero Cross Enable (Bits 4:3) .................................................................. 33
7.8.2 Analog Input Selection (Bits 2:0) ........................................................................................... 34
7.9 Active Level Control - Address 0Ch ................................................................................................ 34
7.9.1 Active High/ Low (Bit 0) ......................................................................................................... 34
7.10 Status - Address 0Dh ................................................................................................................... 34
7.10.1 Clock Error (Bit 3) ................................................................................................................ 35
7.10.2 Overflow (Bit 1) .................................................................................................................... 35
7.10.3 Underflow (Bit 0) .................................................................................................................. 35
7.11 Status Mask - Address 0Eh .......................................................................................................... 35
7.12 Status Mode MSB - Address 0Fh ................................................................................................. 35
7.13 Status Mode LSB - Address 10h .................................................................................................. 35
8. PARAMETER DEFINITIONS ................................................................................................................ 36
9. FILTER PLOTS ..................................................................................................................................... 37
10. PACKAGE DIMENSIONS .................................................................................................................. 39
11. THERMAL CHARACTERISTICS AND SPECIFICATIONS .............................................................. 39
12. ORDERING INFORMATION .............................................................................................................. 40
13. REVISION HISTORY .......................................................................................................................... 40
LIST OF FIGURES
Figure 1.Master Mode Serial Audio Port Timing ....................................................................................... 17
Figure 2.Slave Mode Serial Audio Port Timing ......................................................................................... 17
Figure 3.Format 0, 24-Bit Data Left-Justified ............................................................................................ 17
Figure 4.Format 1, 24-Bit Data IS ............................................................................................................ 17
Figure 5.Control Port Timing - IC Format ................................................................................................. 18
Figure 6.Control Port Timing - SPI Format ................................................................................................ 19
Figure 7.Typical Connection Diagram ....................................................................................................... 20
Figure 8.Master Mode Clocking ................................................................................................................ 22
Figure 9.Analog Input Architecture ............................................................................................................ 23
Figure 10.CS5346 PGA ............................................................................................................................ 24
Figure 11.1 VRMS Input Circuit .................................................................................................................. 24
Figure 12.1 VRMS Input Circuit with RF Filtering ....................................................................................... 24
Figure 13.2 VRMS Input Circuit .................................................................................................................. 24
Figure 14.Control Port Timing in SPI Mode .............................................................................................. 26
Figure 15.Control Port Timing, IC Write ................................................................................................... 26
Figure 16.Control Port Timing, IC Read ................................................................................................... 27
Figure 17.Single-Speed Stopband Rejection ............................................................................................ 37
Figure 18.Single-Speed Stopband Rejection ............................................................................................ 37
Figure 19.Single-Speed Transition Band (Detail) ...................................................................................... 37
Figure 20.Single-Speed Passband Ripple ................................................................................................ 37
Figure 21.Double-Speed Stopband Rejection ........................................................................................... 37
Figure 22.Double-Speed Stopband Rejection ........................................................................................... 37
Figure 23.Double-Speed Transition Band (Detail) .................................................................................... 38
Figure 24.Double-Speed Passband Ripple ............................................................................................... 38
Figure 25.Quad-Speed Stopband Rejection ............................................................................................. 38
Figure 26.Quad-Speed Stopband Rejection ............................................................................................. 38
Figure 27.Quad-Speed Transition Band (Detail) ....................................................................................... 38
Figure 28.Quad-Speed Passband Ripple ................................................................................................. 38
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