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| 型号： | CS5361GD16 |
| 厂商： | ON SEMICONDUCTOR |
| 元件分类： | 稳压器 |
| 英文描述： | 2 A BATTERY CHARGE CONTROLLER, 635 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封装： | SOIC-16 |
| 文件页数： | 5/15页 |
| 文件大小： | 120K |
| 代理商： | CS5361GD16 |
CS5361
http://onsemi.com
1243
closed loop control–to–output transfer function without and
with compensation is shown in Figure 5.
Figure 5. Bode Plot of Control–to–Output
Transfer Function
dB
With Compensation
–1
–2
f
–3
Without Compensation
fs/2
If a transconductance amplifier is used as the error
amplifier, the integrator pole can be implemented by
connecting a capacitor from the amplifier output to the
ground. The compensation gain is given by:
FC(s) +
G
(sCCOMP)
(63)
where G is the transconductance of the amplifier.
The total loop gain is
T(s)
+
G
RI
sCCOMP 1.0 ) s (wnQ) ) s2 wn2
(64)
The value of the compensation capacitor CCOMP can be
calculated if the crossover frequency is known. Generally,
the crossover frequency should be chosen well below the
switching frequency.
We can choose
fCO + 1 6
fS
So
CCOMP +
G
RI
2.0
pfCO
(65)
7. Design of Voltage Compensation Network
For voltage, “control” is referred to the output of the
Voltage Error Amplifier (VCOMP) and “output” is the output
voltage. The control–to–output transfer function with
closed current loop is given by:
VOUT
VCOMP
[
R(1.0
) sC
ESR)
RI(1.0 ) sCR) 1.0 ) s (wnQ) ) s2 wn2
(66)
Compare the above expression with equation (60), the
transfer function of current mode voltage control has same
poles as I2 control. The difference is the zero. For I2 control,
the zero is determined by both ESR of the output capacitor
and the load resistor and can be cancel out the low frequency
pole. But for current mode voltage control, the zero is a high
frequency ESR zero. The low frequency pole cannot be
cancelled. So the system is third–order. The Bode plot of the
control–to–output transfer function with closed current loop
is illustrated in Figure 6
Figure 6. Bode Plot
dB
Low Freq. Pole
–1
–2
Double Pole
ESR Zero
f
For a transconductance error amplifier, a possible
compensation network is shown in Figure 7. The
compensation network has two poles and one zero.
Figure 7. Compensation Network
VFB
–
+
VREF(IN)
R1
C1
C2
VCOMP
The compensation gain is given by:
F(s)
+
G
(1.0
) sR1C1)
(C1
) C2)
s[1.0
) sR1C1C2 (C1 ) C2)]
(67)
The integrator pole will give the system high DC gain. Use
the zero to compensate the excessive phase delay caused by
the low frequency pole of the control–to–output transfer
function. The other pole of the compensation network
should be placed around the ESR zero to make sure the
amplitude decrease fast after the 0 dB crossover.
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