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| 型号： | CS5463-ISZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 27/46页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METERING 1PHASE 24SSOP |
| 特色产品： | CS546X IC Family |
| 标准包装： | 59 |
| 输入阻抗： | 30 千欧 |
| 测量误差： | 0.1% |
| 电压 - 高输入/输出： | 0.8V |
| 电压 - 低输入/输出： | 0.2V |
| 电流 - 电源： | 2.9mA |
| 电源电压： | 4.75 V ~ 5.25 V |
| 测量仪表类型： | 单相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 24-SSOP |
| 包装： | 管件 |
| 产品目录页面： | 754 (CN2011-ZH PDF) |
| 配用： | 598-1553-ND - BOARD EVAL & SOFTWARE CS5463 ADC |
| 其它名称： | 598-1096-5 |
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CS5463
6.1.2 Current and Voltage DC Offset Register ( I DCoff , V DCoff )
Address: 1 (Current DC Offset); 3 (Voltage DC Offset)
MSB
LSB
-(2 )
2
2
2
2
2
0
2
-1
2
-2
-3
-4
-5
-6
-7
.....
2 -17
2
-18
2
-19
2
-20
2
-21
2
-22
2 -23
Default = 0x000000
The DC Offset registers (I DCoff ,V DCoff ) are initialized to 0.0 on reset. When DC Offset calibration is performed, the
register is updated with the DC offset measured over a computation cycle. DRDY will be set at the end of the
calibration. This register may be read and stored for future system offset compensation. The value is represent-
ed in two's complement notation and in the range of -1.0 ? I DCoff , V DCoff ? 1.0, with the binary point to the right of
the MSB. See Section 7.1.2.1 DC Offset Calibration Sequence on page 37 for more information.
6.1.3 Current and Voltage Gain Register ( I gn , V gn )
Address: 2 (Current Gain); 4 (Voltage Gain)
MSB
LSB
2 1
2 0
2 -1
2 -2
2 -3
2 -4
2 -5
2 -6
.....
2 -16
2 -17
2 -18
2 -19
2 -20
2 -21
2 -22
Default = 0x400000 = 1.000
The gain registers (I gn ,V gn ) are initialized to 1.0 on reset. When either a AC or DC Gain calibration is performed,
the register is updated with the gain measured over a computation cycle. DRDY will be set at the end of the
calibration. This register may be read and stored for future system gain compensation. The value is in the range
0.0 ? I gn ,V gn < 3.9999, with the binary point to the right of the second MSB.
6.1.4 Cycle Count Register ( Cycle Count )
Address: 5
MSB
LSB
2 23
2 22
2 21
2 20
2 19
2 18
2 17
2 16
.....
2 6
2 5
2 4
2 3
2 2
2 1
2 0
Default = 0x000FA0 = 4000
Cycle Count, denoted as N, determines the length of one computation cycle . During continuous conversions,
the computation cycle frequency is (MCLK/K)/(1024 ? N). A one second computational cycle period occurs when
MCLK = 4.096 MHz, K = 1, and N = 4000.
6.1.5 PulseRateE Register ( PulseRateE )
Address: 6
MSB
LSB
-(2 0 )
2 -1
2 -2
2 -3
2 -4
2 -5
2 -6
2 -7
.....
2 -17
2 -18
2 -19
2 -20
2 -21
2 -22
2 -23
Default = 0x800000 = 1.00 (2 kHz @ 4.096 MHz MCLK)
PulseRateE sets the frequency of E1, E2, & E3 pulses. E1, E2, E3 frequency = (MCLK x PulseRateE) / 2048 at
full scale. For a 4 khz sample rate, the maximum pulse rate is 2 khz. The value is represented in two's comple-
ment notation and in the range is -1.0 ? PulseRateE ? 1.0, with the binary point to the right of the MSB. Negative
values have the same effect as positive. See Section 5.5 Energy Pulse Output on page 17 for more information.
DS678F3
27
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS5463-ISZ/D | 制造商:Cirrus Logic 功能描述: |
| CS5463-ISZR | 功能描述:电流和电力监控器、调节器 IC Single Phase PWR/Energy RoHS:否 制造商:STMicroelectronics 产品:Current Regulators 电源电压-最大:48 V 电源电压-最小:5.5 V 工作温度范围:- 40 C to + 150 C 安装风格:SMD/SMT 封装 / 箱体:HPSO-8 封装:Reel |
| CS5463-ISZR/E2 | 制造商:Cirrus Logic 功能描述: |
| CS5464 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:Three-channel, Single-phase Power/Energy IC |
| CS5464_07 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:Three-channel, Single-phase Power/Energy IC |
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