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| 型号： | CS5529-ASZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 11/31页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT W/6BIT LATCH 20SSOP |
| 标准包装： | 66 |
| 位数： | 16 |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 3.5mW |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个差分，单极；1 个差分，双极 |
| 产品目录页面： | 755 (CN2011-ZH PDF) |
| 配用： | 598-1015-ND - EVAL BOARD FOR CS5529 |
| 其它名称： | 598-1110-5 |
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CS5529
DS246F5
19
tions). If a system gain calibration is performed, the
calibrated input must not cause the resulting gain
register’s content, decoded in decimal, to exceed
3.9999998. The above condition requires that the
full scale input voltage to be greater than 25 percent
of the differential reference voltage (i.e. a 625mV
input signal must be applied if the differential ref-
erence voltage is 2.5V).
Limitations in Calibration Range
System calibration can be limited by signal head-
room in the analog signal path inside the chip as
discussed under the Analog Input section of this
data sheet. For gain calibration the full scale input
signal can be reduced to the point in which the gain
register reaches its upper limit of (4-2-22 decimal)
or FFFFFF (hexadecimal). Under nominal condi-
tions, this occurs with a full scale input signal equal
to about 1/4 the reference voltage. With the con-
verter’s intrinsic gain error, this full scale input sig-
nal may be higher or lower. In defining the
minimum Full Scale Calibration Range (FSCR)
under “Analog Characteristics”, margin is retained
to accommodate the intrinsic gain error. Alterna-
tively the input full scale signal can be increased to
a point which exceeds the operating range of the
analog circuitry. This occurs when the input volt-
age is approximately 1.5X the differential refer-
ence voltage (Gain Register = 1.0).
Calibration Tips
Calibration steps are performed at the output word
rate selected by the WR2-WR0 bits of the configu-
ration register. Since higher word rates result in
conversion words with more peak-to-peak noise,
calibration should be performed at lower output
word rates. Also, to minimize digital noise near the
device, the user should wait for each calibration
step to be completed before reading or writing to
the serial port.
Factory calibration can be performed in a user’s
system by using the system calibration capabilities
of the CS5529. After the ADC is calibrated in the
user’s system, the offset and gain register contents
can be read by the system microcontroller and re-
corded in EEPROM. These same calibration words
can then be uploaded into the offset and gain regis-
ters of the converter when power is first applied to
the system.
A user can scale the input range by modifying the
gain register. For example, if a self or system cali-
bration is performed with a full scale of 2.5 V and
a full scale of 1.25 V is desired, the user can modify
the gain register to double its slope. This can be
done by reading the gain register, shifting the bina-
ry word one position to the left (this multiplies the
gain word by 2), and writing this word back into the
gain register. The gain register can be scaled by any
amount as long as it does not exceed a decimal
range of 0.25 to 4.0.
One of two methods can be used to determine when
a calibration is complete: 1) if the PF (Port Flag) bit
of the configuration register is set to logic 1, SDO
falls to logic 0 at the completion of a calibration; or
2) regardless of the PF bit, the DF (Done Flag) bit
in the configuration register is set at completion of
calibration. The user can either monitor the DF bit
or SDO to determine when a calibration is com-
plete. Whichever method is used, the calibration
control bits (CC2-CC0) automatically return to log-
ic 0 upon completion of any calibration.
+
-
External
Connections
Full Scale
+
-
AIN+
AIN-
Figure 9. System Calibration of Gain.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS5529-ASZR | 功能描述:模数转换器 - ADC IC Prgrmbl Dlt Sigma ADC w/6-Bit Latch RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| CS5530 | 制造商:Texas Instruments 功能描述: |
| CS5530_0911 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:24-bit ADC with Ultra-low-noise Amplifier |
| CS5530A | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:AMD Geode CS5530A Companion Device |
| CS5530A-UCE | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:AMD Geode CS5530A Companion Device |
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