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| 型号： | CS5533-ASZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 26/43页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT PGIA 2-CH 24-SSOP |
| 标准包装： | 59 |
| 位数： | 16 |
| 采样率（每秒）： | 3.84k |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 45mW |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 24-SSOP |
| 包装： | 管件 |
| 输入数目和类型： | 4 个差分，单极；4 个差分，双极 |
| 产品目录页面： | 755 (CN2011-ZH PDF) |
| 其它名称： | 598-1114-5 |
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CS5531/32/33/34-AS
32
DS289F5
2.5.6. System Calibration
For the system calibration functions, the user must
supply the converter’s calibration signals which rep-
resent ground and full scale. When a system offset
calibration is performed, a ground-referenced signal
must be applied to the converters. Figure 13 illus-
trates system offset calibration.
As shown in Figure 14, the user must input a signal
representing the positive full-scale point to perform
a system gain calibration. In either case, the cali-
bration signals must be within the specified calibra-
tion limits for each specific calibration step (refer
to the System Calibration Specifications).
2.5.7. Calibration Tips
Calibration steps are performed at the output word
rate selected by the WR2-WR0 bits of the channel
setup registers. Due to limited register lengths in
the faster word-rate filters (240 Sps and higher),
channels that are used at these rates should also be
calibrated in one of these word rates, and channels
used in the lower word rates (120 Sps and lower)
should be calibrated at one of these lower rates.
Since higher word rates result in conversion words
with more peak-to-peak noise, calibration should
be performed at the lowest possible output word
rate for maximum accuracy. For the 7.5 Sps to 120
Sps word rate settings, calibrations can be per-
formed at 7.5 Sps, and for 240 Sps and higher, cal-
ibration can be performed at 240 Sps. To minimize
digital noise near the device, the user should wait
for each calibration step to be completed before
reading or writing to the serial port. Reading the
calibration registers and averaging multiple cali-
brations together can produce a more accurate cal-
ibration result. Note that accessing the ADC’s
serial port before a calibration has finished may re-
sult in the loss of synchronization between the mi-
+
_
AIN+
AIN-
1X GAIN
Figure 11. Self-calibration of Offset
AIN+
AIN-
OPEN
+
-
XGAIN
+
-
OPEN
CLOSED
VREF+
CLOSED
VREF-
+
-
Reference
Figure 12. Self-calibration of Gain
+
-
XGAIN
+
-
External
Connections
0V
+
-
AIN+
AIN-
CM +
-
Figure 13. System Calibration of Offset
+
-
XGAIN
+
-
External
Connections
Full Scale +
-
AIN+
AIN-
CM +
-
Figure 14. System Calibration of Gain
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS5533-ASZ/H1 | 制造商:Cirrus Logic 功能描述: |
| CS5533-ASZR | 功能描述:模数转换器 - ADC IC 16-Bit ADCs w/UltraLw Noise PGIA RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| CS5534 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:16 BIT AND 24 BIT ADCS WITH ULTRA LOW NOISE PGIA |
| CS5534-AS | 功能描述:模数转换器 - ADC 4-Ch 24-Bit ADCs w/ Ultra Low Noise PGIA RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| CS5534-ASR | 功能描述:模数转换器 - ADC IC 24-Bit ADCs w/UltraLw Noise PGIA RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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