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参数资料
| 型号： | CS7666-KQ |
| 厂商： | CRYSTAL SEMICONDUCTOR CORP |
| 元件分类： | 消费家电 |
| 英文描述： | DIGITAL COLOR-SPACE PROCESSOR FOR CCD CAMERAS |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封装： | TQFP-64 |
| 文件页数： | 21/42页 |
| 文件大小： | 676K |
| 代理商： | CS7666-KQ |
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CS7666
DS302PP1
21
Master Reset Register (00h)
MR
Setting bit MR0 to logic high will initiate a CS7666 master reset equivalent to executing an ex-
ternal reset using the RESET pin. All registers will be placed in their default state, and the down-
load of any external EPROM present on the secondary I
2
C bus will be initiated. The bit is self-
cleared.
Status Register (01h)
EVNFLD
Logic high indicates even field of interline-transfer CCD. Logic low indicates odd field of inter-
line-transfer CCD. This bit provides a course means of synchronizing to the field rate.
NODEV
Logic high indicates that the addressed slave device on the secondary I
2
C bus did not respond.
I2CBUSY
Logic high indicates that the CS7666 secondary I
2
C master is busy accessing the addressed
slave device.
INITACT
Logic high indicates the CS7666 master is busy initializing registers from the external I
2
C
EPROM on the secondary I
2
C bus (if present).
HIZENB
Pin 63 status.
INTERP
Pin 54 status.
P4BYTE
Pin 1 status.
PIN I/O Control (02h)
PLLOUT
Logic high enables the PLL clock output to the CS7615 (pin 51). This pin was a NC on the
CS7665.
FIELDOUT
Logic high changes FIELD (pin 62) from an input to an output pin. Default is input.
UV_ENB
Logic high replaces FIELD with a U/V clock.
Digital Gain Register (03h)
DG[4:0]
Controls the digital gain applied to the Y (Luminance) signal after the RGB to YCrCb converter
block. The range of gains are from 0 to 31/8 in increments of 1/8. A gain of 0, indicates no bright-
ness.
7
6
5
4
3
2
1
0
res
res
res
res
res
res
res
MR
W
Reserved
7
6
5
4
3
2
1
0
res
P4BYTE
R
INTERP
R
HIZENB
R
INITACT
R
I2CBUSY
R
NODEV
R
EVNFLD
R
Reserved
7
6
5
4
3
2
1
0
res
res
res
res
res
UV_ENB
R/W
FIELDOUT
R/W
PLLOUT
R/W
Reserved
7
6
5
4
3
2
1
0
res
res
res
DG4
DG3
DG2
R/W
DG1
DG0
Reserved
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