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参数资料
| 型号： | CS7666-KQ |
| 厂商： | CRYSTAL SEMICONDUCTOR CORP |
| 元件分类： | 消费家电 |
| 英文描述： | DIGITAL COLOR-SPACE PROCESSOR FOR CCD CAMERAS |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封装： | TQFP-64 |
| 文件页数： | 37/42页 |
| 文件大小： | 676K |
| 代理商： | CS7666-KQ |
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CS7666
DS302PP1
37
CLKOUT - Digital Output Data Clock, PIN 59.
Digital output clock for both channel "A" and channel "B." Output data transitions on the
falling edge of CLKOUT and can be latched on the rising edge. In the non-interleaved output
mode, the CLKOUT rate is equal to the input mosaic pixel rate multiplied by the scaling ratio
currently in use with Y data available on channel "A" and CrCb output data on Channel "B." In
interleaved output mode, the CLKOUT rate is equal to twice the input mosaic pixel rate
multiplied by the current scaling ratio with Y and CrCb output data available on Channel "A".
INTERP - Digital Video Horizontal Data Rate Scaler Enable, PIN 54.
CMOS input enabling the internal 4:5 horizontal data rate scaler when the CS7666 is in
CS7665 compatibility mode (default.) Requires that CLKIN2 be supplied with a 5/2 rate clock
relative to the CLKIN clock input which is the incoming CCD mosaic data. This pin control is
active logic high. This pin is ignored in CS7666 native mode.
HREFOUT - Horizontal Reference Output, PIN 30.
CMOS output providing HREF, or alternatively HSYNC horizontal blanking signal.
VREFOUT - Vertical Reference Output, PIN 31.
CMOS output providing a VREF, or alternatively VSYNC vertical blanking signal.
FIELD - Odd/Even Field Indicator, PIN 62.
CMOS input/output. As an input, the field pin synchronizes the EAV/SAV timing codes
embedded in the output video datastream. As an output, the FIELD indicator changes according
to the embedded EAV/SAV timing codes in the input video datastream or the HREFIN and
VREFIN inputs. Odd fields are indicated with logic low, and even fields are indicated with
logic high. Alternately, the Field pin can be configured as a U/V clock.
OE - Output Enable, PIN 63.
CMOS input used to place all output pins in a High-Z mode. This control works in conjunction
with the OE bit (bit 3)in register 06h.
Output Mode
Mosaic
Data Rate
9.818 MHz 9.818 MHz 19.63 MHz
9.818 MHz 9.818 MHz 24.54 MHz
9.818 MHz 9.818 MHz 19.63 MHz
9.818 MHz 9.818 MHz 24.54 MHz
Table 16. Example 512x492 Imager Output Options
(4:5 scaling ratio chosen)
CLKIN
CLKIN2
Channel
“A”
YcrCb
YcrCb
Y
Y
Channel
"B”
logic "0” 19.63 MHz
logic "0” 24.54 MHz
CrCb
9.818 MHz
CrCb
12.27 MHz
CLKOUT Horizontal
Pixels
512
640
512
640
Interleaved, scaler disabled
Interleaved, scaler enabled
Parallel, scaler disabled
Parallel, scaler enabled
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