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参数资料
| 型号： | CS7666-KQ |
| 厂商： | CRYSTAL SEMICONDUCTOR CORP |
| 元件分类： | 消费家电 |
| 英文描述： | DIGITAL COLOR-SPACE PROCESSOR FOR CCD CAMERAS |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封装： | TQFP-64 |
| 文件页数： | 24/42页 |
| 文件大小： | 676K |
| 代理商： | CS7666-KQ |
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CS7666
24
DS302PP1
Operational Control Register II (07h)
HS_SEL
Logic 1 causes HSYNC to be output on pin 31. Logic low causes HREF (horizontal blank) to be
output on pin 31.
VS_SEL
L.ogic 1 causes VSYNC to be output on pin 30. Logic low causes VREF (vertical blank) to be
output on pin 30.
H_INV
Logic 1 inverts the polarity of pin 31.
V_INV
Logic 1inverts the polarity of pin 30.
H_SFT[1:0]
Shifts the the signal on pin 30 from 0 to 3 clock cycles.
CLIP_OFF
When set, excludes only 00 and FF from output data. Otherwise ITU BT
TEST_AA
This bit is reserved for test purposes and may be set as a 1 or a 0.
Red Balance Register (08h)
RB[7:0]
The Red Balance register controls the red contribution to the R-Y chrominance signal. When
the register value is 00h, the red contribution is minimized; when the register value is FFh, the
red contribution is maximized. When the AWB correction is in progress, this register value is
adjusted such that the absolute magnitude of the R-Y signal is minimized.
Blue Balance Register (09h)
BB[7:0]
The Blue Balance register controls the blue contribution to the B-Y chrominance signal. When
the register value is 00h, the blue contribution is minimized; when the register value is FFh, the
blue contribution is maximized. When the AWB correction is in progress, this register value is
adjusted such that the absolute magnitude of the B-Y signal is minimized.
Red Saturation Register (0Ah)
RS[7:0]
The Red Saturation register value controls the amplitude of the R-Y chrominance signal. When
the register value is 00h, the amplitude of the R-Y is minimized; when the register value is FFh,
the amplitude of the R-Y is maximized.
7
6
5
4
3
2
1
0
TEST_AA
R/W
CLIP_OFF
R/W
H_SFT1
H_SFT0
V_INV
R/W
H_INV
R/W
VS_SEL
R/W
HS_SEL
R/W
R/W
7
6
5
4
3
2
1
0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
R/W
7
6
5
4
3
2
1
0
BB7
BB6
BB5
BB4
BB3
BB2
BB1
BB0
R/W
7
6
5
4
3
2
1
0
RS7
RS6
RS5
RS4
RS3
RS2
RS1
RS0
R/W
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