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参数资料
| 型号： | CS7666-KQ |
| 厂商： | CRYSTAL SEMICONDUCTOR CORP |
| 元件分类： | 消费家电 |
| 英文描述： | DIGITAL COLOR-SPACE PROCESSOR FOR CCD CAMERAS |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封装： | TQFP-64 |
| 文件页数： | 35/42页 |
| 文件大小： | 676K |
| 代理商： | CS7666-KQ |
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CS7666
DS302PP1
35
Input Data and Clocks
DI[9:0] - Digital Mosaic Inputs.
CMOS level mosaic coded CCD input data from CCD digitizer
CLKIN - Mosaic Input Data Clock, PIN 55.
Main system input clock, used to strobe incoming digital CCD mosaic data. The CLKIN
frequency is the mosaic input data rate.
CLKIN2X - Mosaic Input Data Interpolation Clock, PIN 56.
Mosaic input data interpolation clock or crystal oscillator input. Twice the CLKIN input in
CS7665 compatibility mode (non-interpolated output data ... see INTERP description). Twice
the 5/4 output rate clock when internal 5 to 4 horizontal data rate scaler is in operation
(CS7665 compatibility mode.) In CS7666 native mode, this pin operates as the crystal oscillator
input pin. The required crystal frequency is 2 X (SCALER RATIO) X (INPUT DATA RATE).
For example a 512x492 pixel imager running at 9.818 MHz and scaled by a factor of 5:4
would require 2 X (5/4) X (9.818) = 24.54 MHz.
CLK_GRG - CCD Sample Clock, PIN 51.
This clock is scaled by the internal PLL and is equal to the CLKIN2X frequency divided by the
scaling ratio. This clock is intended to connect to the CS7615 master clock pin (pin 32).
XTAL_OUT – Crystal oscillator output, PIN 52.
When using the internal crystal oscillator, connect the external crystal to the XTAL_OUT and
CLKIN2X pins.
HREFIN - Horizontal Input Timing Reference, PIN 32.
Active low horizontal input timing reference. Used to synchronize the output timing signals
with the incoming mosaic data and timing. When used with CCD digitizers like the CS7615
which imbed the necessary timing signals in the data stream, the HREFIN signal is not needed.
VREFIN - Vertical Input Timing Reference, PIN 33.
Active low vertical input timing reference. Used to synchronize the output timing signals with
the incoming mosaic data and timing. When used with CCD digitizers like the CS7615 which
embed the necessary timing signals in the data stream, the VREFIN signal is not needed.
I
2
C Serial Control
SDA - Primary I
2
C Data Bus, PIN 28.
Primary I
2
C data bus. Used with SCL to read and write the internal register set.
SCL - Primary I
2
C Clock, PIN 29.
Primary I
2
C Clock. Used with SDA to read and write the internal register set.
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