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| 型号： | CY22393 |
| 厂商： | Cypress Semiconductor Corp. |
| 元件分类： | 8位微控制器 |
| 英文描述： | -bit AVR Microcontroller with 8K Bytes In- System Programmable Flash |
| 中文描述： | 位AVR微控制器具有8K字节的系统内可编程闪存 |
| 文件页数： | 4/19页 |
| 文件大小： | 246K |
| 代理商： | CY22393 |
CY22393
CY22394
CY22395
Document #: 38-07186 Rev. *B
Page 4 of 19
Operation
The CY22393, CY22394, and CY22395 are a family of parts
designed as upgrades to the existing CY22392 device. These
parts have similar performance to the CY22392, but provide
advanced features to meet the needs of more demanding
applications.
The clock family has three PLLs which, when combined with
the reference, allow up to four independent frequencies to be
output on up to six pins. These three PLLs are completely
programmable.
Configurable PLLs
PLL1 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL1 is sent
to two locations: the cross point switch and the PECL output
(CY22394). The output of PLL1 is also sent to a /2, /3, or /4
synchronous post-divider that is output through CLKE. The
frequency of PLL1 can be changed via serial programming or
by external CMOS inputs, S0, S1, and S2. See the following
section on general-purpose Inputs for more detail.
PLL2 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL2 is sent
to the cross point switch. The frequency of PLL2 can be
changed via serial programming.
PLL3 generates a frequency that is equal to the reference
divided by an 8-bit divider (Q) and multiplied by an 11-bit
divider in the PLL feedback loop (P). The output of PLL3 is sent
to the cross point switch. The frequency of PLL3 can be
changed via serial programming.
General-Purpose Inputs
S2 is a general-purpose input that can be programmed to
allow for two different frequency settings. Options that may be
switched with this general-purpose input are as follows: the
frequency of PLL1, the output divider of CLKB, and the output
divider of CLKA.
The two frequency settings are contained within an eight-row
frequency table. The values of SCLK (S1) and SDAT (S0) pins
are latched during start-up and used as the other two indexes
into this array.
CLKA and CLKB both have 7-bit dividers that point to one of
two programmable settings (register 0 and register 1). Both
clocks share a single register control, so both must be set to
register 0, or both must be set to register 1.
For example, the part may be programmed to use S0, S1, and
S2 (0,0,0 to 1,1,1) to control eight different values of P and Q
on PLL1. For each PLL1 P and Q setting, one of the two CLKA
and CLKB divider registers can be chosen. Any divider change
as a result of switching S0, S1, or S2 is guaranteed to be glitch
free.
Crystal Input
The input crystal oscillator is an important feature of this family
of parts because of its flexibility and performance features.
The oscillator inverter has programmable drive strength. This
allows for maximum compatibility with crystals from various
manufacturers, process, performance, and quality.
The input load capacitors are placed on-die to reduce external
component cost. These capacitors are true parallel-plate
capacitors for ultra-linear performance. These were chosen to
reduce the frequency shift that occurs when non-linear load
capacitance interacts with load, bias, supply, and temperature
changes. Non-linear (FET gate) crystal load capacitors should
not be used for MPEG, POTS dial tone, communications, or
other applications that are sensitive to absolute frequency
requirements.
The value of the load capacitors is determined by six bits in a
programmable register. The load capacitance can be set with
a resolution of 0.375 pF for a total crystal load range of 6 pF
to 30 pF.
For driven clock inputs the input load capacitors may be
completely bypassed. This enables the clock chip to accept
driven frequency inputs up to 166 MHz. If the application
requires a driven input, then XTALOUT must be left floating.
Digital VCXO
The serial programming interface may be used to dynamically
change the capacitor load value on the crystal. A change in
crystal load capacitance corresponds with a change in the
reference frequency.
For special pullable crystals specified by Cypress, the capac-
itance pull range is +150 ppm to –150 ppm from midrange.
CLKA or LCLKA
10
10
10
Configurable clock output A; LCLKA referenced to LVDD
GND/LGND
11
11
11
Ground
SDAT (S0)
12
12
12
Two Wire Serial Port Data. S0 value latched during start-up
SCLK (S1)
13
13
13
Two Wire Serial Port Clock. S1 value latched during start-up
AV
DD
S2/
SUSPEND
14
14
14
Analog Power Supply
15
15
15
General Purpose Input for Frequency Control; bit 2. Optionally
Suspend mode control input
SHUTDOWN/
OE
16
16
16
Places outputs in three-state condition and shuts down chip
when LOW. Optionally, only places outputs in three-state
condition and does not shut down chip when LOW
Pin Definitions
(continued)
Name
Pin Number
CY22393
Pin Number
CY22394
Pin Number
CY22395
Description
相关PDF资料 |
PDF描述 |
|---|---|
| CY22394 | -bit AVR Microcontroller with 8K Bytes In- System Programmable Flash |
| CY2254A | Pentium Processor Compatible Clock Synthesizer/Driver(奔腾处理器兼容的时钟合成器/驱动器) |
| CY2254 | Two-PLL Clock Generator(二锁相环时钟发生器) |
| CY2256 | Pentium and Cyrix 6x86 Compatible Clock Synthesizer/Driver for OPTi Viper Chipset(应用于 OPTi Viper芯片组的奔腾和 Cyrix公司 6x86兼容的时钟合成器/驱动器) |
| CY2273A | Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop PCs with Intel 82430TX, 82440LX or ALI IV/IV+, AGP and 3 DIMMs |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY22393_09 | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Three-PLL Serial-Programmable Flash-Programmable Clock Generator |
| CY223931 | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Three-PLL Serial-Programmable Flash-Programmable Clock Generator |
| CY223931FXI | 功能描述:时钟发生器及支持产品 3-PLL Flash Clk Gen 1MHz-166MHz RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| CY22393FC | 功能描述:IC CLKSYN SRL/FLASH 3PLL 16TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| CY22393FCT | 制造商:Cypress Semiconductor 功能描述:Programmable PLL Clock Generator Triple 16-Pin TSSOP T/R |
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