参数资料
型号: CY28346ZXC
厂商: Silicon Laboratories Inc
文件页数: 15/19页
文件大小: 0K
描述: IC CLOCK DIFF OUT CK408 56TSSOP
标准包装: 35
类型: *
PLL:
输入: 晶体
输出: 时钟
电路数: 1
比率 - 输入:输出: 1:19
差分 - 输入:输出: 无/是
频率 - 最大: 200MHz
除法器/乘法器: 是/无
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 70°C
安装类型: *
封装/外壳: *
供应商设备封装: *
包装: *
其它名称: SLCY28346ZXC
CY28346
........................Document #: 38-07331 Rev. *C Page 5 of 19
Byte 6: Silicon Signature Register[4] (all bits are Read-only)
Bit
@Pup
Pin#
Description
7
0
Revision = 0001
60
50
41
3
0
Vendor Code = 0011
20
11
01
Byte 7: Reserved Register
Bit
@Pup
Pin#
Description
7
0
Reserved. Set = 0.
6
0
Reserved. Set = 0.
5
0
Reserved. Set = 0.
4
0
Reserved. Set = 0.
3
0
Reserved. Set = 0.
2
0
Reserved. Set = 0.
1
0
Reserved. Set = 0.
0
Reserved. Set = 0.
Byte 8: Dial-a-Frequency Control Register N
Bit
@Pup
Name
Description
7
0
Reserved. Set = 0.
6
0
N6, MSB
These bits are for programming the PLL’s internal N register. This access allows the user to
modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks
(clocks that are generated from the same PLL, such as PCI) remain at their existing ratios
relative to the CPU clock.
50
N5
40
N4
30
N3
20
N2
10
N3
00
N0, LSB
Byte 9: Dial-a-Frequency Control Register R
Bit
@Pup
Name
Description
70
Reserved. Set = 0.
6
0
R5, MSB
These bits are for programming the PLL’s internal R register. This access allows the user to
modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks
(clocks that are generated from the same PLL, such as PCI) remain at their existing ratios
relative to the CPU clock.
50
R4
40
R3
30
R2
20
R1
10
R0
00
DAF_ENB
R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is loaded
from DAF (SMBus) registers.
Note:
4. When writing to this register, the device will acknowledge the Write operation, but the data itself will be ignored.
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