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参数资料
| 型号： | CY28447LFXCT |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 12/22页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CALISTOGA CK410M 72QFN |
| 标准包装： | 2,000 |
| 类型： | 时钟/频率发生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服务器 |
| 输入： | LVTTL，晶体 |
| 输出： | HCSL，LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:21 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 200MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 72-VFQFN 裸露焊盘 |
| 供应商设备封装： | 72-QFN（10x10） |
| 包装： | 带卷 (TR) |
CY28447
........................ Document #: 38-07724 Rev *C Page 2 of 22
Pin Description
Pin No.
Name
Type
Description
1, 49, 54, 65 VDD_SRC
PWR
3.3V power supply for outputs.
2, 3, 50, 51,
52, 53, 55,
56, 58, 59,
60, 61, 63,
64, 66, 67,
69, 70
SRCT/C[1:9]
O, DIF 100-MHz Differential serial reference clocks.
4, 68
VSS_SRC
GND
Ground for outputs.
5, 6
CPUT2_ITP/SRCT10,
CPUC2_ITP/SRCC10
O, DIF Selectable differential CPU or SRC clock output.
ITP_SEL = 0 @ VTT_PWRGD# assertion = SRC10
ITP_SEL = 1 @ VTT_PWRGD# assertion = CPU2
7
VDDA
PWR
3.3V power supply for PLL.
8
VSSA
GND
Ground for PLL.
9IREF
I
A precision resistor is attached to this pin which is connected to the internal
current reference.
10, 11, 13, 14 CPUT/C[0:1]
O, DIF Differential CPU clock outputs.
12
VDD_CPU
PWR
3.3V power supply for outputs.
15
VSS_CPU
GND
Ground for outputs.
16
SCLK
I
SMBus-compatible SCLOCK.
17
SDATA
I/O, OD SMBus-compatible SDATA.
18
VDD_REF
PWR
3.3V power supply for outputs.
19
XOUT
O, SE 14.318-MHz crystal output.
20
XIN
I
14.318-MHz crystal input.
21
VSS_REF
GND
Ground for outputs.
22
REF1
O
Fixed 14.318-MHz clock output.
23
REF0/FSC_TESTSEL I/O,PD Fixed 14.318 clock output / 3.3V-tolerant input for CPU frequency
selection/Selects test mode if pulled to VIMFS_C when VTT_PWRGD# is
asserted LOW.
Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifi-
cations.
24
CPU_STP#
I, PU
3.3V LVTTL input for CPU_STP# active LOW.
25
PCI_STP#
I, PU
3.3V LVTTL input for PCI_STP# active LOW.
26, 28, 29,
38, 46, 57,
62, 71, 72
CLKREQ[1:9]#
I, PU
3.3V LVTTL input for enabling assigned SRC clock (active LOW).
27, 32, 33
PCI[1:3]
O, SE 33-MHz clock outputs
30, 36
VDD_PCI
PWR
3.3V power supply for outputs.
31, 35
VSS_PCI
GND
Ground for outputs.
34
PCI4/FCTSEL1
I/O, PD 33-MHz clock output / 3.3V LVTTL input for selecting pins 47,48 (SRC[T/C]0,
100M[T/C]) and pins 43,44 (DOT96[T/C] and 27M Spread and Non-spread)
(sampled on the VTT_PWRGD# assertion).
37
ITP_SEL/PCIF0
I/O,PD,
SE
3.3V LVTTL input to enable SRC10 or CPU2_ITP / 33-MHz clock output.
(sampled on the VTT_PWRGD# assertion).
1 = CPU2_ITP, 0 = SRC10
FCTS E L1 P in 43
P in 44
P in 47
P in 48
0 DOT96T
DOT96C
96/100M_T 96/100M_C
1 27M_NSS
27M_SS
SRCT0
SRCC0
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