参数资料
型号: CY28447LFXCT
厂商: Silicon Laboratories Inc
文件页数: 15/22页
文件大小: 0K
描述: IC CLOCK CALISTOGA CK410M 72QFN
标准包装: 2,000
类型: 时钟/频率发生器
PLL:
主要目的: Intel CPU 服务器
输入: LVTTL,晶体
输出: HCSL,LVCMOS
电路数: 1
比率 - 输入:输出: 3:21
差分 - 输入:输出: 无/是
频率 - 最大: 200MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 72-VFQFN 裸露焊盘
供应商设备封装: 72-QFN(10x10)
包装: 带卷 (TR)
CY28447
...................... Document #: 38-07724 Rev *C Page 22 of 22
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil-
icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the
use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or
parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, repre-
sentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli-
cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Document History Page
Document Title: CY28447 Clock Generator for IntelCalistoga Chipset
Document Number: 38-07724
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
315554
See ECN
RGL
New data sheet
*A
345509
See ECN
RGL
Changed VTTPWRGD#/PD changed from PU to PD.
Change Advance to Preliminary status
*B
381616
See ECN
RGL
Modify pin description table
Update register table
Modify AC specification of 27-MHz LACC to 0 ppm
*C
391400
See ECN
RGL
Update block diagram to show the 4th PLL
Add Figure 15 and 16 for single-ended load configuration
Update DC Electrical Specification table
Update AC Electrical Specification table
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