- 您现在的位置：买卖IC网 > PDF目录380137 > CY39200V256-233MBC (Cypress Semiconductor Corp.) CPLDs at FPGA Densities PDF资料下载
参数资料
| 型号： | CY39200V256-233MBC |
| 厂商： | Cypress Semiconductor Corp. |
| 英文描述： | CPLDs at FPGA Densities |
| 中文描述： | CPLD器件在FPGA的密度 |
| 文件页数： | 19/86页 |
| 文件大小： | 1235K |
| 代理商： | CY39200V256-233MBC |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页当前第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 19 of 86
Cluster Memory Timing Parameter Descriptions
Over the Operating Range
t
CKIN
t
IOREGPIN
PLL Parameters
t
MCCJ
t
DWSA
t
DWOSA
t
LOCK
t
INDUTY
f
PLLI
f
PLLO
f
PLLVCO
P
SAPLLI
f
MPLLI
Delay from the clock pin to the input of the clock driver
Delay from the I/O pin to the input of the I/O register
Maximum cycle to cycle jitter time
PLL zero phase delay with clock tree deskewed
PLL zero phase delay without clock tree deskewed
Lock time for the PLL
Input duty cycle
Input frequency of the PLL
Output frequency of the PLL
PLL VCO frequency of operation
Percentage modulation allowed (spread awareness) on the PLL input clock
Frequency of modulation allowed on PLL input clock. This specifies how fast the f
PLLI
sweeps between f
PLLI
*
(1–P
SAPLLI
/100) and f
PLLI
* (1+ P
SAPLLI
/100)
JTAG Parameters
t
JCKH
TCLK HIGH time
t
JCKL
TCLK LOW time
t
JCP
TCLK clock period
t
JSU
JTAG port set-up time (TDI/TMS inputs)
t
JH
JTAG port hold time (TDI/TMS inputs)
t
JCO
JTAG port clock to output time (TDO)
t
JXZ
JTAG port valid output to high impedance (TDO)
t
JZX
JTAG port high impedance to valid output (TDO)
Switching Characteristics — Parameter Descriptions
Over the Operating Range
[13]
(continued)
Parameter
Description
Parameter
Asynchronous Mode Parameters
t
CLMAA
t
CLMPWE
t
CLMSA
t
CLMHA
t
CLMSD
t
CLMHD
Synchronous Mode Parameters
t
CLMCYC1
Description
Cluster memory access time. Delay from address change to Read data out
Write Enable pulse width
Address set-up to the beginning of Write Enable with both signals from the same I/O block
Address hold after the end of Write Enable with both signals from the same I/O block
Data set-up to the end of Write Enable
Data hold after the end of Write Enable
Clock cycle time for flow through Read and Write operations (from macrocell register through cluster memory
back to a macrocell register in the same cluster)
Clock cycle time for pipelined Read and Write operations (from cluster memory input register through the
memory to cluster memory output register)
Address, data, and WE set-up time of pin inputs, relative to a global clock
Address, data, and WE hold time of pin inputs, relative to a global clock
Global clock to data valid on output pins for flow through data
Global clock to data valid on output pins for pipelined data
Cluster memory input clock to macrocell clock in the same cluster
Cluster memory output clock to macrocell clock in the same cluster
Macrocell clock to cluster memory input clock in the same cluster
t
CLMCYC2
t
CLMS
t
CLMH
t
CLMDV1
t
CLMDV2
t
CLMMACS1
t
CLMMACS2
t
MACCLMS1
相关PDF资料 |
PDF描述 |
|---|---|
| CY39200V256-233MBI | CPLDs at FPGA Densities |
| CY39200V256-233NC | CPLDs at FPGA Densities |
| CY39200V256-233NI | CPLDs at FPGA Densities |
| CY39200V256-233NTI | CPLDs at FPGA Densities |
| CY39200V256-83BBC | CPLDs at FPGA Densities |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY39200V256-233MGC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200V256-233MGI | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200V256-233NTC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200V388-125MGC | 功能描述:IC CPLD 200K GATE 388-BGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - CPLD（复杂可编程逻辑器件） 系列:Delta 39K™ ISR™ 标准包装:40 系列:ispMACH® 4000C 可编程类型:系统内可编程 最大延迟时间 tpd(1):5.0ns 电压电源 - 内部:1.65 V ~ 1.95 V 逻辑元件/逻辑块数目:32 宏单元数:512 门数:- 输入/输出数:128 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:176-LQFP 供应商设备封装:176-TQFP（24x24） 包装:托盘 |
| CY39200V388-181MGC | 制造商:Cypress Semiconductor 功能描述: |
发布紧急采购，3分钟左右您将得到回复。