参数资料
型号: CY7C09099V-6AXC
厂商: CYPRESS SEMICONDUCTOR CORP
元件分类: SRAM
英文描述: 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
中文描述: 128K X 8 DUAL-PORT SRAM, 15 ns, PQFP100
封装: ROHS COMPLIANT, PLASTIC, MS-026, TQFP-100
文件页数: 2/20页
文件大小: 599K
代理商: CY7C09099V-6AXC
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document #: 38-06043 Rev. *E
Page 10 of 20
Figure 9. Left Port Write to Flow-Through Right Port Read[22, 23, 24, 25]
Notes
20. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet. ADDRESS(B1)
= ADDRESS(B2).
21. OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
22. The same waveforms apply for a right port write to flow-through left port read.
23. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
24. OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to.
25. It tCCS maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum specified, then data is not valid
until tCCS + tCD1. tCWDD does not apply in this case.
Switching Waveforms (continued)
tSA
tHA
tSW
tHW
tSD
tHD
MATCH
VALID
tCCS
tSW
tHW
tDC
tCWDD
tCD1
MATCH
tSA
tHA
MATCH
NO
MATCH
NO
VALID
tDC
tCD1
CLKL
R/WL
ADDRESSL
DATAINL
ADDRESSR
DATAOUTR
CLKR
R/WR
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CY7C09099V-7AI 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
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