参数资料
型号: CY7C09099V-6AXC
厂商: CYPRESS SEMICONDUCTOR CORP
元件分类: SRAM
英文描述: 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
中文描述: 128K X 8 DUAL-PORT SRAM, 15 ns, PQFP100
封装: ROHS COMPLIANT, PLASTIC, MS-026, TQFP-100
文件页数: 9/20页
文件大小: 599K
代理商: CY7C09099V-6AXC
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document #: 38-06043 Rev. *E
Page 17 of 20
Table 1. Read/Write and Enable Operation[34, 35, 36]
Inputs
Outputs
OE
CLK
CE0
CE1
R/W
I/O0–I/O9
Operation
X
H
X
High-Z
Deselected[37]
X
L
X
High-Z
Deselected[37]
X
L
H
L
DIN
Write
L
H
DOUT
Read[37]
H
X
L
H
X
High-Z
Outputs Disabled
Table 2. Address Counter Control Operation[34, 38, 39, 40]
Address Previous
Address
CLK
ADS
CNTEN CNTRST
I/O
Mode
Operation
X
L
Dout(0)
Reset
Counter Reset to Address 0
An
X
L
X
H
Dout(n)
Load
Address Load into Counter
X
An
H
Dout(n)
Hold
External Address Blocked—Counter
Disabled
X
An
H
L
H
Dout(n+1)
Increment
Counter Enabled—Internal Address
Generation
Notes
34. “X” = “Don’t Care”, “H” = VIH, “L” = VIL.
35. ADS, CNTEN, CNTRST = “Don’t Care.”
36. OE is an asynchronous input signal.
37. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle.
38. CE0 and OE = VIL; CE1 and R/W = VIH.
39. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
40. Counter operation is independent of CE0 and CE1.
相关PDF资料
PDF描述
CY7C09099V-7AI 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
CY7C09099V-12AXC 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
CY7C09099V-7AXI 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
CY7C09179V-12AXC 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
CY7C09179V-6AXC 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
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