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参数资料
| 型号： | CY7C09159AV-12AXC |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | SRAM |
| 英文描述： | 3.3V 8K/16K x 9 Synchronous Dual Port Static RAM |
| 中文描述： | 8K X 9 DUAL-PORT SRAM, 25 ns, PQFP100 |
| 封装： | PLASTIC, LEAD FREE, TQFP-100 |
| 文件页数： | 11/16页 |
| 文件大小： | 526K |
| 代理商： | CY7C09159AV-12AXC |
CY7C09159AV
CY7C09169AV
Document #: 38-06053 Rev. *B
Page 4 of 16
Maximum Ratings[4]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65
°C to +150°C
Ambient Temperature with Power Applied ..–55
°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
DC Voltage Applied to
Outputs in High Z State............................–0.5V to VCC+0.5V
DC Input Voltage......................................–0.5V to VCC+0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
Latch-Up Current ..................................................... >200 mA
Note:
4. The voltage on any input or I/O pin can not exceed the power pin during power-up
5. Industrial parts are available in CY7C09169AV only.
Pin Definitions
Left Port
Right Port
Description
A0L–A13L
A0R–A13R
Address Inputs (A0A12 for 8K; A0A13 for 16K devices).
ADSL
ADSR
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW during
normal read or write transactions. Asserting this signal LOW also loads the burst address counter
with data present on the I/O pins.
CE0L,CE1L
CE0R,CE1R
Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to
their active states (CE0 ≤ VIL and CE1 ≥ VIH).
CLKL
CLKR
Clock Signal. This input can be free-running or strobed. Maximum clock input rate is fMAX.
CNTENL
CNTENR
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
CNTRSTL
CNTRSTR
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O8L
I/O0R–I/O8R
Data Bus Input/Output (I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices).
OEL
OER
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
R/WL
R/WR
Read/Write Enable Input. This signal is asserted LOW to write to the dual-port memory array. For
read operations, assert this pin HIGH.
FT/PIPEL
FT/PIPER
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
GND
Ground Input.
NC
No Connect.
VCC
Power Input.
Operating Range
Range
Ambient
Temperature
VCC
Commercial
0
°C to +70°C
3.3V ± 300 mV
Industrial[5]
–40
°C to +85°C
3.3V ± 300 mV
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CY7C09159AV-9AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C09159AV-9AXC | 功能描述:静态随机存取存储器 3.3V 8Kx9 COM Sync Dual Port 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| CY7C09169AV-12AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C09169AV-12AI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C09169AV-12AXC | 功能描述:IC SRAM 144KBIT 12NS 100LQFP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:移动 SDRAM 存储容量:256M（8Mx32） 速度:133MHz 接口:并联 电源电压:1.7 V ~ 1.95 V 工作温度:-40°C ~ 85°C 封装/外壳:90-VFBGA 供应商设备封装:90-VFBGA（8x13） 包装:带卷 (TR) 其它名称:557-1327-2 |
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