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参数资料
| 型号： | CY7C09159AV-12AXC |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | SRAM |
| 英文描述： | 3.3V 8K/16K x 9 Synchronous Dual Port Static RAM |
| 中文描述： | 8K X 9 DUAL-PORT SRAM, 25 ns, PQFP100 |
| 封装： | PLASTIC, LEAD FREE, TQFP-100 |
| 文件页数： | 9/16页 |
| 文件大小： | 526K |
| 代理商： | CY7C09159AV-12AXC |
CY7C09159AV
CY7C09169AV
Document #: 38-06053 Rev. *B
Page 2 of 16
Functional Description
The CY7C09159AV and CY7C09169AV are high-speed
synchronous CMOS 8K and 16K x 9 dual-port static RAMs.
Two ports are provided, permitting independent, simultaneous
access for reads and writes to any location in memory.[2]
Registers on control, address, and data lines allow for minimal
set-up and hold times. In pipelined output mode, data is regis-
tered for decreased cycle time. Clock to data valid tCD2 = 9 ns
(pipelined). Flow-through mode can also be used to bypass
the pipelined output register to eliminate access latency. In
flow-through mode data will be available tCD1 = 18 ns after the
address is clocked into the device. Pipelined output or
flow-through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address
register. The internal write pulse width is independent of the
LOW- to-HIGH transition of the clock signal. The internal write
pulse is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clock cycle will power
down the internal circuitry to reduce the static power
consumption. The use of multiple Chip Enables allows easier
banking of multiple chips for depth expansion configurations.
In the pipelined mode, one cycle is required with CE0 LOW and
CE1 HIGH to reactivate the outputs.
Counter enable inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Note:
2. When simultaneously writing to the same location, final value cannot be guaranteed.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CY7C09159AV-9AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C09159AV-9AXC | 功能描述:静态随机存取存储器 3.3V 8Kx9 COM Sync Dual Port 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| CY7C09169AV-12AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C09169AV-12AI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C09169AV-12AXC | 功能描述:IC SRAM 144KBIT 12NS 100LQFP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:1,000 系列:- 格式 - 存储器:RAM 存储器类型:移动 SDRAM 存储容量:256M（8Mx32） 速度:133MHz 接口:并联 电源电压:1.7 V ~ 1.95 V 工作温度:-40°C ~ 85°C 封装/外壳:90-VFBGA 供应商设备封装:90-VFBGA（8x13） 包装:带卷 (TR) 其它名称:557-1327-2 |
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