参数资料
| 型号： | CYW305OXCT |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 14/20页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK W305 SOLANO 56SSOP |
| 标准包装： | 1,000 |
| 类型： | 时钟/频率发生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服务器 |
| 输入： | 晶体 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:15 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 200MHz |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-BSSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 56-SSOP |
| 包装： | 带卷 (TR) |
W305B
........................ Document #: 38-07262 Rev. *B Page 3 of 20
Overview
The W305B is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel archi-
tecture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation
Upon power-up the power on strap option pins act as a logic
input. An external 10-k
strapping resistor should be used.
Figure 1 shows a suggested method for strapping resistor
connections.
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below
target but will increase to target once supply voltage has stabi-
lized. In either case, a short output clock cycle may be
produced from the CPU clock outputs when the outputs are
enabled.
Offsets Among Clock Signal Groups
relationship among the different groups of clock outputs from
W305B under different frequency modes.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
QD
W305B
Clock Load
Output
Buffer
10 k
Output
Low
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Figure 2. Group Offset Waveforms (66-MHz CPU Clock, 100-MHz SDRAM Clock)
CPU 66-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC 16.6-MHz
0 ns
CPU 66 Period
SDRAM 100 Period
Hub-PCI
40 ns
30 ns
20 ns
10 ns
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