参数资料
型号: CYW305OXCT
厂商: Silicon Laboratories Inc
文件页数: 9/20页
文件大小: 0K
描述: IC CLOCK W305 SOLANO 56SSOP
标准包装: 1,000
类型: 时钟/频率发生器
PLL:
主要目的: Intel CPU 服务器
输入: 晶体
输出: 时钟
电路数: 1
比率 - 输入:输出: 1:15
差分 - 输入:输出: 无/是
频率 - 最大: 200MHz
电源电压: 2.375 V ~ 3.465 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 56-BSSOP(0.295",7.50mm 宽)
供应商设备封装: 56-SSOP
包装: 带卷 (TR)
W305B
...................... Document #: 38-07262 Rev. *B Page 17 of 20
Notes:
4. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.
5. The time specified is measured from when VDDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable and
operating within specification.
6. TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification.
7. TLOW is measured at 0.4V for all outputs.
8. THIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
AC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2= 2.5V±5%fXTL = 14.31818 MHz
Parameter
Description
66.6-MHz Host
100-MHz Host
133-MHz Host
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
TPeriod
Host/CPUCLK Period
15.0
15.5
10.0
10.5
7.5
8.0
ns
THIGH
Host/CPUCLK High Time
5.2
N/A
3.0
N/A
1.87
N/A
ns
TLOW
Host/CPUCLK Low Time
5.0
N/A
2.8
N/A
1.67
N/A
ns
5
TRISE
Host/CPUCLK Rise Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TFALL
Host/CPUCLK Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TPeriod
SDRAM CLK Period
10.0
10.5
10.0
10.5
10.0
10.5
ns
THIGH
SDRAM CLK High Time
3.0
N/A
3.0
N/A
3.0
N/A
ns
4
TLOW
SDRAM CLK Low Time
2.8
N/A
2.8
N/A
2.8
N/A
ns
5
TRISE
SDRAM CLK Rise Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TFALL
SDRAM CLK Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TPeriod
APIC CLK Period
60.0
64.0
60.0
N/A
60.0
64.0
ns
THIGH
APIC CLK High Time
25.5
N/A
25.5
N/A
25.5
N/A
ns
4
TLOW
APIC CLK Low Time
25.3
N/A
25.30
N/A
25.30
N/A
ns
5
TRISE
APIC CLK Rise Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TFALL
APIC CLK Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TPeriod
3V66 CLK Period
15.0
16.0
15.0
16.0
15.0
16.0
ns
THIGH
3V66 CLK High Time
5.25
N/A
5.25
N/A
5.25
N/A
ns
4
TLOW
3V66 CLK Low Time
5.05
N/A
5.05
N/A
5.05
N/A
ns
5
TRISE
3V66 CLK Rise Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
TFALL
3V66 CLK Fall Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
TPeriod
PCI CLK Period
30.0
N/A
30.0
N/A
30.0
N/A
ns
THIGH
PCI CLK High Time
12.0
N/A
12.0
N/A
12.0
N/A
ns
4
TLOW
PCI CLK Low Time
12.0
N/A
12.0
N/A
12.0
N/A
ns
5
TRISE
PCI CLK Rise Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
TFALL
PCI CLK Fall Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
tpZL, tpZH
Output Enable Delay (All outputs)
1.0
10.0
1.0
10.0
1.0
10.0
ns
tpLZ, tpZH
Output Disable Delay
(All outputs)
1.0
10.0
1.0
10.0
1.0
10.0
ns
tstable
All Clock Stabilization from
Power-Up
33
3
ms
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