参数资料
型号: DAC8412FPZ
厂商: Analog Devices Inc
文件页数: 7/20页
文件大小: 0K
描述: IC DAC 12BIT QUAD W/READBK 28DIP
产品培训模块: Data Converter Fundamentals
DAC Architectures
产品变化通告: DAC8412/3 Redesign and Fab Process Change 01/Oct/2009
标准包装: 13
设置时间: 6µs
位数: 12
数据接口: 并联
转换器数目: 4
电压电源: 单电源
功率耗散(最大): 330mW
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 28-DIP(0.600",15.24mm)
供应商设备封装: 28-PDIP
包装: 管件
输出数目和类型: 4 电压,单极;4 电压,双极
采样率(每秒): 167k
Data Sheet
DAC8412/DAC8413
Rev. G | Page 15 of 20
RESET
The RESET function can be used either at power-up or at any
time during DAC operation. The RESET function is independent
of CS. This pin is active low and sets the DAC output registers
to either center code for the DAC8412, or zero code for the
DAC8413. The reset-to-center code is most useful when the
DAC is configured for bipolar references and an output of 0 V
after reset is desired.
SUPPLIES
Supplies required are VSS, VDD, and VLOGIC. The VSS supply can
be set between 15 V and 0 V. VDD is the positive supply; its
operating range is between 5 V and 15 V.
VLOGIC is the digital output supply voltage for the readback
function. It is normally connected to +5 V. This pin is a logic
reference input only. It does not supply current to the device. If
the readback function is not being used, VLOGIC can be left open-
circuit. While VLOGIC does not supply current to the DAC8412, it
does supply currents to the digital outputs when readback is used.
AMPLIFIERS
Unlike many voltage output DACs, the DAC8412 features buffered
voltage outputs. Each output is capable of both sourcing and
sinking 5 mA at ±10 V, eliminating the need for external
amplifiers when driving 500 pF or smaller capacitive load in
most applications. These amplifiers are short-circuit protected.
Table 6. DAC8412/DAC8413 Logic Table
A1
A0
R/W
CS
RS
LDAC
Input Register
Output Register
Mode
DAC
L
H
L
Write
Transparent
A
L
H
L
H
L
Write
Transparent
B
H
L
H
L
Write
Transparent
C
H
L
H
L
Write
Transparent
D
L
H
Write
Hold
Write input
A
L
H
L
H
Write
Hold
Write input
B
H
L
H
Write
Hold
Write input
C
H
L
H
Write
Hold
Write input
D
L
H
L
H
Read
Hold
Read input
A
L
H
L
H
Read
Hold
Read input
B
H
L
H
L
H
Read
Hold
Read input
C
H
L
H
Read
Hold
Read input
D
X
H
L
Hold
Update all output registers
All
X
H
Hold
All
X
L
X
All registers reset to midscale/zero-scale1
All
X
H
X
All registers latched to midscale/zero-scale1
All
1
DAC8412 resets to midscale, and DAC8413 resets to zero scale. L = logic low; H = logic high; X = don’t care. Input and output registers are transparent when asserted.
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