参数资料
型号: DAC8564IAPWG4
厂商: TEXAS INSTRUMENTS INC
元件分类: DAC
英文描述: SERIAL INPUT LOADING, 12 us SETTLING TIME, 16-BIT DAC, PDSO16
封装: GREEN, PLASTIC, TSSOP-16
文件页数: 20/51页
文件大小: 1549K
代理商: DAC8564IAPWG4
DAC
Register
REF(+)
ResistorString
REF( )
-
V
L
REF
V
H
REF
V
OUTX
62kW
50kW
V
OUTX + 2
V
REFL
) (VREFH * VREFL)
D
IN
65536
V
REF
R
V
REF
2
R
DIVIDER
ToOutputAmplifier
(2xGain)
SBAS403D
– JUNE 2007 – REVISED MAY 2011
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER (DAC)
The DAC8564 architecture consists of a string DAC
followed by an output buffer amplifier. Figure 92
shows a block diagram of the DAC architecture.
Figure 92. DAC8564 Architecture
The input coding to the DAC8564 is straight binary,
so the ideal output voltage is given by Equation 1.
(1)
where DIN = decimal equivalent of the binary code
that is loaded to the DAC register; it can range from 0
to 65535. X represents channel A, B, C, or D.
RESISTOR STRING
The resistor string section is shown in Figure 93. It is
simply a string of resistors, each of value R. The
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
Figure 93. Resistor String
be fed into the output amplifier by closing one of the
switches connecting the string to the amplifier. It is
monotonic because it is a string of resistors.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating
rail-to-rail voltages on its output, giving an output
range of 0V to AVDD. It is capable of driving a load of
2k
in parallel with 1000pF to GND. The source and
sink capabilities of the output amplifier can be seen in
the Typical Characteristics. The slew rate is 2.2V/
μs,
with a full-scale settling time of 8
μs with the output
unloaded.
Copyright
2007–2011, Texas Instruments Incorporated
27
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