参数资料
型号: DAC8564IAPWG4
厂商: TEXAS INSTRUMENTS INC
元件分类: DAC
英文描述: SERIAL INPUT LOADING, 12 us SETTLING TIME, 16-BIT DAC, PDSO16
封装: GREEN, PLASTIC, TSSOP-16
文件页数: 26/51页
文件大小: 1549K
代理商: DAC8564IAPWG4
V
X
OUT
Amplifier
Resistor
String
DAC
Power-Down
Circuitry
Resistor
Network
SBAS403D
– JUNE 2007 – REVISED MAY 2011
POWER-DOWN MODES
DACs. However, for the three power-down modes,
the supply current falls to 1.3
μA at 5.5V (0.5μA at
The DAC8564 has two separate sets of power-down
3.6V). Not only does the supply current fall, but the
commands. One set is for the DAC channels and the
output stage also switches internally from the output
other set is for the internal reference. For more
of the amplifier to a resistor network of known values.
information on powering down the reference, see the
The advantage of this switching is that the output
impedance of the device is known while it is in
DAC Power-Down Commands
power-down mode. As described in Table 6, there are
three different power-down options. VOUT can be
The DAC8564 uses four modes of operation. These
connected internally to GND through a 1k
resistor, a
modes are accessed by setting three bits (PD2, PD1,
100k
resistor, or open circuited (High-Z). The output
and PD0) in the shift register. Table 6 shows how to
stage is shown in Figure 96. In other words, DB16,
control the operating mode with data bits PD0
DB15, and DB14 = '111' represent a power-down
(DB16), PD1 (DB15), and PD2 (DB14).
condition with Hi-Z output impedance for a selected
channel. '101' represents a power-down condition
Table 6. DAC Operating Modes
with 1k
output impedance, and '110' represents a
PD0
PD1
PD2
power-down condition with 100k
output impedance.
(DB16)
(DB15)
(DB14)
DAC OPERATING MODES
0
X
Normal operation
1
0
1
Output typically 1k
to GND
1
0
Output typically 100 k
to GND
1
Output high-impedance
The DAC8564 treats the power-down condition as
data; all the operational modes are still valid for
power-down. It is possible to broadcast a power-down
condition to all the DAC8564s in a system; it is also
possible to simultaneously power-down a channel
while updating data on other channels.
Figure 96. Output Stage During Power-Down
When the PD0 bit is set to '0', the device works
normally with its typical current consumption of 1mA
All analog channel circuitries are shut down when the
at 5.5V with an input code = 32768. The reference
power-down
mode
is
exercised.
However,
the
current is included with the operation of all four
contents of the DAC register are unaffected when in
power down. The time required to exit power-down is
typically 2.5
μs for VDD = 5V, and 5μs for VDD = 3V.
See the Typical Characteristics for more information.
32
Copyright
2007–2011, Texas Instruments Incorporated
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