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参数资料
型号： DAC8564IAPWG4
厂商： TEXAS INSTRUMENTS INC
元件分类： DAC
英文描述： SERIAL INPUT LOADING, 12 us SETTLING TIME, 16-BIT DAC, PDSO16
封装： GREEN, PLASTIC, TSSOP-16
文件页数： 27/51页
文件大小： 1549K
代理商： DAC8564IAPWG4
DAC8564
www.ti.com
SBAS403D
– JUNE 2007 – REVISED MAY 2011
OPERATING EXAMPLES: DAC8564
For the following examples, ensure that DAC pins A0 and A1 are both connected to ground. Pins A0 and A1
must always match data bits DB22 and DB23 within the SPI write sequence/protocol. X = don't care. Value can
be either '0' or '1'.
Example 1: Write to Data Buffer A Through Buffer D; Load DAC A Through DAC D Simultaneously
1st: Write to data buffer A:
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
–DB0
(A1)
(A0)
(LD1)
(LD0)
(DAC Sel 1) (DAC Sel 0)
(PD0)
0
D15
D14
D13
D12
D11
–D0
2nd: Write to data buffer B:
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
–DB0
(A1)
(A0)
(LD1)
(LD0)
(DAC Sel 1) (DAC Sel 0)
(PD0)
0
1
0
D15
D14
D13
D12
D11
–D0
3rd: Write to data buffer C:
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
–DB0
(A1)
(A0)
(LD1)
(LD0)
(DAC Sel 1) (DAC Sel 0)
(PD0)
0
1
0
D15
D14
D13
D12
D11
–D0
4th: Write to data buffer D and simultaneously update all DACs:
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
–DB0
(A1)
(A0)
(LD1)
(LD0)
(DAC Sel 1) (DAC Sel 0)
(PD0)
0
1
0
1
0
D15
D14
D13
D12
D11
–D0
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon
completion of the 4th write sequence. (The DAC voltages update simultaneously after the 24th SCLK falling edge
of the fourth write cycle).
Example 2: Load New Data to DAC A Through DAC D Sequentially
1st: Write to data buffer A and load DAC A: DAC A output settles to specified value upon completion:
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
–DB0
(A1)
(A0)
(LD1)
(LD0)
(DAC Sel 1) (DAC Sel 0)
(PD0)
0
1
0
D15
D14
D13
D12
D11
–D0
2nd: Write to data buffer B and load DAC B: DAC B output settles to specified value upon completion:
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
–DB0
(A1)
(A0)
(LD1)
(LD0)
(DAC Sel 1) (DAC Sel 0)
(PD0)
0
1
0
1
0
D15
D14
D13
D12
D11
–D0
3rd: Write to data buffer C and load DAC C: DAC C output settles to specified value upon completion:
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
–DB0
(A1)
(A0)
(LD1)
(LD0)
(DAC Sel 1) (DAC Sel 0)
(PD0)
0
1
0
1
0
D15
D14
D13
D12
D11
–D0
4th: Write to data buffer D and load DAC D: DAC D output settles to specified value upon completion:
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
–DB0
(A1)
(A0)
(LD1)
(LD0)
(DAC Sel 1) (DAC Sel 0)
(PD0)
0
1
0
1
0
D15
D14
D13
D12
D11
–D0
After completion of each write cycle, DAC analog output settles to the voltage specified.
Copyright
2007–2011, Texas Instruments Incorporated
33
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