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参数资料
型号： DAC8571IDGKR
厂商： TEXAS INSTRUMENTS INC
元件分类： DAC
英文描述： SERIAL INPUT LOADING, 13 us SETTLING TIME, 16-BIT DAC, PDSO8
封装： GREEN, PLASTIC, MSOP-8
文件页数： 15/30页
文件大小： 825K
代理商： DAC8571IDGKR
www.ti.com
Power-On Reset
Power-Down Modes
DAC8571
SLAS373A – DECEMBER 2002 – REVISED JULY 2003
EXAMPLE 11: Read back DAC8571 internal data. V denotes valid logic.
ADDRESS<7...0>
M<7...0>
MASTER
L<7...0>
MASTER
C<7...0>
MASTER
START
1001 1001
ACK
VVVV VVVV
ACK
VVVV VVVV
ACK
VVVV VVVV NOT ACK STOP
EXAMPLE 12: Ramp generation in high speed mode (up to code 7 is shown)
HS Master Code
ADDRESS
C<7...0>
START
0000 1000
NOT ACK
REPEATED START
1001 1000
ACK
0001 0000
ACK
Previous Vout voltage valid
MSB<7...0>
LSB<7...0>
MSB<7...0>
LSB<7...0>
0000 0000
ACK
0000 0000
ACK
0000 0000
ACK
0000 0001
ACK
Previous Vout voltage valid
Vout = 0 V
Vout = 76 V
MSB<7...0>
LSB<7...0>
MSB<7...0>
LSB<7...0>
0000 0000
ACK
0000 0010
ACK
0000 0000
ACK
0000 0011
ACK
Vout = 76 V
Vout = 2
×76 V
Vout = 3
×76 V
MSB<7...0>
LSB<7...0>
MSB<7...0>
LSB<7...0>
0000 0000
ACK
0000 0100
ACK
0000 0000
ACK
0000 0101
ACK
Vout = 3
×76 V
Vout = 4
×76 V
Vout = 5
×76 V
MSB<7...0>
LSB<7...0>
MSB<7...0>
LSB<7...0>
0000 0000
ACK
0000 0110
ACK
0000 0000
ACK
0000 0111
ACK
Vout = 5
×76 V
Vout = 6
×76 V
Vout = 7
×76 V
The DAC8571 contains a power-on-reset circuit that controls the output voltage during power-up. On power-up,
the DAC register is filled with zeros and the output voltage is 0V; it remains there until a valid write sequence is
made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC
while it is in the process of powering up. No input is brought high before the power is applied.
The DAC8571 contains five separate power settings. These modes are programmable when C<0>=1. When
C<0>=1, M<7>, M<6>, and M<5> bits represent power setting control bits, and M<4...0> and L<7...0> are
assigned to zeroes. Power setting of DAC8571 is updated at the falling edge of the acknowledge signal that
follows the least significant byte. To set the power consumption of the device, following I
2C sequence is used.
Start_condition ->
Valid_address
(1001 1000) -> ack
C<7:0>
(0001 0001) -> ack
M<7:0>
( vvv0 0000) -> ack
L<7:0>
(0000 0000) -> ack
Stop_condition
Table 6. Power Settings for the DAC8571 (C<0>=1)
M<7>
M<6>
M<5>
Operating Mode
0
Low power mode, default
0
1
Fast settling mode
0
1
X
PWD. 1k
to GND
1
0
X
PWD. 100 k
to GND
1
X
PWD. Output Hi-Z
22
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