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参数资料
| 型号： | DAC8571IDGKR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 13 us SETTLING TIME, 16-BIT DAC, PDSO8 |
| 封装： | GREEN, PLASTIC, MSOP-8 |
| 文件页数： | 8/30页 |
| 文件大小： | 825K |
| 代理商： | DAC8571IDGKR |
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Master Reading From a Slave Transmitter (Standard/Fast Modes)
Master Writing to a Slave Receiver (High-Speed Mode)
DAC8571
SLAS373A – DECEMBER 2002 – REVISED JULY 2003
I
2C protocol starts when the bus is idle, that is, when SDA and SCL lines are stable high. The master then pulls
the SDA line low while SCL is still high indicating that serial data transfer has started. This is called a start
condition, and can only be asserted by the master. After the start condition, the master generates the serial clock
pulses and puts out an address byte, ADDRESS<7:0>. While generating the bit stream, the master ensures the
timing for valid data. For each valid I
2C bit, SDA line should remain stable during the entire high period of the
SCL line. The address byte consists of seven address bits (1001100, assuming A0=0) and a direction bit
(R/W=1). After sending the address byte, the master generates a 9
th SCL pulse and monitors the state of the
SDA line during the high period of this 9
th clock cycle (master leaves the SDA line high). The SDA line being
pulled low by a receiver during the high period of 9
th clock cycle is called an acknowledge signal. If the master
receives an acknowledge signal, it knows that a DAC8571 successfully matched the address the master sent.
Since the R/W bit in the address byte was set, master also knows that DAC8571 is ready to transmit data. Upon
the receipt of this acknowledge, the master knows that the communication link with a DAC8571 has been
established and more data could be received. The master continues by sending eight clock cycles during which
DAC8571 transmits a most significant byte, M<7:0>. If the master detects all bits of the M<7:0> as valid data, it
sends an acknowledge signal in the 9
th cycle. DAC8571 detects this acknowledge signal and prepares to send
more data. Upon the receipt of eight clock cycles from the master, DAC8571 transmits the least significant byte
L<7:0>. If the master detects all bits of the L<7:0> as valid data, it sends an acknowledge signal to DAC8571
during the 9
th clock cycle. DAC8571 detects this acknowledge signal and prepares to send more data. Upon the
receipt of 8 more clock cycles from the master, DAC8571 transmits the control byte C<7:0>. During the 9
th clock
cycle, the master transmits a not-acknowledge signal to DAC8571 and terminates the sequence with a stop
condition, by pulling the SDA line from low to high while clock is high. M<7:0> and L<7:0> data could be either
DAC data or could be the data stored in the temporary register. Bits in the C<7:0> reveal this information.
Table 2 demonstrates the sequence of events that should occur while a master receiver is reading from
DAC8571.
Table 2. Master Receiver Reads From Slave Transmitter (DAC8571)
Standard/Fast Mode Read Sequence-Data Transmit
Transmitter
MSB
6
5
4
3
2
1
LSB
Comment
Master
Start
Begin sequence
Master
1
0
1
A0
0
R/W
Read addressing (R/W = 1)
DAC8571
DAC8571 Acknowledges
DAC8571
D15
D14
D13
D12
D11
D10
D9
D8
High byte
Master
Master Acknowledges
DAC8571
D7
D6
D5
D4
D3
D2
D1
D0
Low byte
Master
Master Acknowledges
DAC8571
C7
C6
C5
C4
C3
C2
C1
C0
Control byte
Master
Master Not Acknowledges
Master signal end of read
Master
Stop or Repeated Start
Done
All devices must start operation in standard/fast mode and switch to high-speed mode using a well defined
protocol. This is required because high-speed mode requires the on chip filter settings of each I
2C device (for
SDA and SCL lines) to be switched to support 3.4 Mbps operation. A stop condition always ends the high speed
mode and puts all devices back to standard/fast mode.
I
2C protocol starts when the bus is idle, that is, when SDA and SCL lines are stable high. The master then pulls
the SDA line low while SCL is still high indicating that serial data transfer has started. This is called a start
condition, and can only be asserted by the master. After the start condition, the master device puts out the
high-speed master code 0000 1xxx. No device is allowed to acknowledge the master code, but the devices are
required to switch their internal settings to support 3.4 Mbps operation upon the receipt of this code. After the
not-acknowledge signal, the master is allowed to operate at high speed. Now at much higher speed, the master
generates a repeated start condition. After the start condition, master generates the serial clock pulses and puts
out an address byte, ADDRESS<7:0>. While generating the bit stream, the master ensures the timing for valid
data. For each valid I
2C bit, SDA line should remain stable during the entire high period of the SCL line. The
address byte consists of seven address bits and a direction bit (R/W=0). After sending the address byte, the
16
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