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参数资料
| 型号： | DAC8571IDGKR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 13 us SETTLING TIME, 16-BIT DAC, PDSO8 |
| 封装： | GREEN, PLASTIC, MSOP-8 |
| 文件页数： | 6/30页 |
| 文件大小： | 825K |
| 代理商： | DAC8571IDGKR |
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Master Writing to a Slave Receiver (Standard/Fast Modes)
DAC8571
SLAS373A – DECEMBER 2002 – REVISED JULY 2003
I
2C protocol starts when the bus is idle, that is, when SDA and SCL lines are stable high. The master then pulls
the SDA line low while SCL is still high indicating that serial data transfer has started. This is called a start
condition, and can only be asserted by the master. After the start condition, the master generates the serial clock
pulses and puts out an address byte, ADDRESS<7:0>. While generating the bit stream, the master ensures the
timing for valid data. For each valid I
2C bit, SDA line should remain stable during the entire high period of the
SCL line. The address byte consists of 7 address bits (1001100, assuming A0=0) and a direction bit (R/W=0).
After sending the address byte, the master generates a 9
th SCL pulse and monitors the state of the SDA line
during the high period of this 9
th clock cycle. The SDA line being pulled low by a receiver during the high period
of 9
th clock cycle is called an acknowledge signal. If the master receives an acknowledge signal, it knows that a
DAC8571 successfully matched the address the master sent. Upon the receipt of this acknowledge, the master
knows that the communication link with a DAC8571 has been established and more data could be sent. The
master continues by sending a control byte C<7:0>, which sets DAC8571's operation mode. After sending the
control byte, the master expects an acknowledge signal. Upon receipt of the acknowledge, the master sends a
most significant byte M<7:0> that represents the eight most significant bits of DAC8571's 16-bit digital-to-analog
conversion data. Upon receipt of the M<7:0>, DAC8571 sends an acknowledge. After receiving the acknowledge,
the master sends a least significant byte L<7:0> that represents the eight least significant bits of DAC8571's
16-bit conversion data. After receiving the L<7:0>, the DAC8571 sends an acknowledge. At the falling edge of
the acknowledge signal following the L<0>, DAC8571 performs a digital to analog conversion. For further DAC
updates, the master can keep repeating M<7:0> and L<7:0> sequences, expecting an acknowledge after each
byte. After the required number of digital-to-analog conversions is complete, the master can break the
communication link with DAC8571 by pulling the SDA line from low to high while SCL line is high. This is called a
stop condition. A stop condition brings the bus back to idle (SDA and SCL both high). A stop condition indicates
that communication with DAC8571 has ended. All devices on the bus including DAC8571 then await a new start
condition followed by a matching address byte. DAC8571 stays at its current state upon receipt of a stop
condition. Table 1 demonstrates the sequence of events that should occur while a master transmitter is writing to
DAC8571.
14
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| DAC8571IDGKRG4 | 功能描述:数模转换器- DAC Lo-Pwr R-To-R Output 16-Bit I2C Input RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
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| DAC8574EVM | 功能描述:数据转换 IC 开发工具 DAC8574 Eval Mod RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| DAC8574IPW | 功能描述:数模转换器- DAC Lo-Pwr Quad R-To-R Out 16-Bit I2C Input RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC8574IPWG4 | 功能描述:数模转换器- DAC Lo-Pwr Quad R-To-R Out 16-Bit I2C Input RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
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