参数资料
型号: DC1018B-B
厂商: Linear Technology
文件页数: 13/26页
文件大小: 0K
描述: DEMO BOARD FOR LT4356-2
设计资源: DC1018B Design File
DC1018B Schematic
标准包装: 1
主要目的: 过压防护
嵌入式:
已用 IC / 零件: LT4356-2
已供物品:
相关产品: LT4356HDE-3-ND - IC REG OVP FAULT TIMER 12DFN
LT4356HS-3#PBF-ND - IC REG OVP W/LATCHOFF 16SOIC
LT4356HMS-3#PBF-ND - IC REG OVP W/LATCHOFF 10-MSOP
LT4356HDE-3#PBF-ND - IC REG OVP W/LATCHOFF 12DFN
LT4356HS-3#TRPBF-ND - IC REG OVP FAULT TIMER 16SOIC
LT4356HMS-3#TRPBF-ND - IC REG OVP FAULT TIMER 10MSOP
LT4356HDE-3#TRPBF-ND - IC REG OVP FAULT TIMER 12DFN
LT4356MPS-2#TRPBF-ND - IC SURGE STOPPER ADJ 16-SOIC
LT4356MPS-1#TRPBF-ND - IC SURGE STOPPER ADJ 16-SOIC
LT4356MPMS-1#TRPBF-ND - IC SURGE STOPPER ADJ 10-MSOP
更多...
LT4356-1/LT4356-2
APPLICATIONS INFORMATION
This ?xed early warning period allows the systems to per-
form necessary backup or house-keeping functions before
the power supply is cut off. After V TMR crosses the 1.35V
threshold, the pass transistor turns off immediately. Note
that during an overcurrent event, the timer current is not
reduced to 5μA after V TMR has reached 1.25V threshold,
since it would lengthen the overall fault timer period and
cause more stress on the power MOSFET.
As soon as the fault condition has disappeared, a 2μA
current starts to discharge the timer capacitor to ground.
When V TMR reaches the 0.5V threshold, the internal charge
pump starts to pull the GATE pin high, turning on the
MOSFET. The TMR pin is then actively regulated to 0.5V
until the next fault condition appears. The total cool down
timer period is given by:
voltage N-channel MOSFETs. For systems with V CC less
than 8V, a logic level MOSFET is required since the gate
drive can be as low as 4.5V.
The SOA of the MOSFET must encompass all fault condi-
tions. In normal operation the pass transistor is fully on,
dissipating very little power. But during either overvoltage
or overcurrent faults, the GATE pin is servoed to regu-
late either the output voltage or the current through the
MOSFET. Large current and high voltage drop across the
MOSFET can coexist in these cases. The SOA curves of
the MOSFET must be considered carefully along with the
selection of the fault timer capacitor.
Transient Stress in the MOSFET
During an overvoltage event, the LT4356 drives a series
t COOL =
C TMR ? 0.85V
2μA
pass MOSFET to regulate the output voltage at an acceptable
level. The load circuitry may continue operating throughout
this interval, but only at the expense of dissipation in the
MOSFET Selection
The LT4356 drives an N-channel MOSFET to conduct the
load current. The important features of the MOSFET are
on-resistance R DS(ON) , the maximum drain-source voltage
V (BR)DSS , the threshold voltage, and the SOA.
The maximum allowable drain-source voltage must be
higher than the supply voltage. If the output is shorted
to ground or during an overvoltage event, the full supply
voltage will appear across the MOSFET.
The gate drive for the MOSFET is guaranteed to be more
than 10V and less than 16V for those applications with V CC
higher than 8V. This allows the use of standard threshold
V PK
τ
V IN
t r
MOSFET pass device. MOSFET dissipation or stress is a
function of the input voltage waveform, regulation voltage
and load current. The MOSFET must be sized to survive
this stress.
Most transient event speci?cations use the model shown
in Figure 3. The idealized waveform comprises a linear
ramp of rise time t r , reaching a peak voltage of V PK and
exponentially decaying back to V IN with a time constant
of t. A common automotive transient speci?cation has
constants of t r = 10μs, V PK = 80V and τ = 1ms. A surge
condition known as “load dump” has constants of t r =
5ms, V PK = 60V and τ = 200ms.
4356 F03
Figure 3. Prototypical Transient Waveform
4356fa
13
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