参数资料
型号: DC1018B-B
厂商: Linear Technology
文件页数: 16/26页
文件大小: 0K
描述: DEMO BOARD FOR LT4356-2
设计资源: DC1018B Design File
DC1018B Schematic
标准包装: 1
主要目的: 过压防护
嵌入式:
已用 IC / 零件: LT4356-2
已供物品:
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LT4356-1/LT4356-2
APPLICATIONS INFORMATION
R SNS
Q2
Q1
V IN
12V
D2*
SMAJ58CA
10mΩ
Si4435
D1
1N5245
15V
IRLR2908
V OUT
12V, 3A
CLAMPED
AT 16V
5
R6
10k
R3
10Ω
4
3
R1
59k
SNS
GATE
OUT
6
V CC
FB
2
R2
4.99k
7
SHDN
LT4356S
11
A OUT
FLT
8
12
IN +
GND
TMR
EN
9
*DIODES INC.
10
1
C TMR
0.1μF
4356 F08
Figure 8. Overvoltage Regulator with P-Channel MOSFET
Reverse Input Protection
Shutdown
The LT4356 can be shut down to a low current mode when
the voltage at the SHDN pin goes below the shutdown
threshold of 0.6V. The quiescent current drops to 7μA for
the LT4356-1 and 60μA for the LT4356-2 which leaves the
auxiliary ampli?er on.
A total bulk capacitance of at least 22μF low ESR electro-
lytic is required close to the source pin of MOSFET Q1. In
addition, the bulk capacitance should be at least 10 times
larger than the total ceramic bypassing capacitor on the
input of the DC/DC converter.
The SHDN pin can be pulled up to V CC or below GND by
up to 60V without damaging the pin. Leaving the pin open
allows an internal current source to pull it up and turn
on the part while clamping the pin to 2.5V. The leakage
V IN
D2
SMAJ58A
R SNS
10mΩ
Q1
IRLR2908
C L *
22μF
current at the pin should be limited to no more than 1μA
if no pull up device is used to help turn it on.
5
R3
10Ω
4
3
R1
59k
V CC
DC-DC
Supply Transient Protection
The LT4356 is guaranteed to be safe from damage with
supply voltages up to 100V. Nevertheless, voltage tran-
sients above 100V may cause permanent damage. During
a short-circuit condition, the large change in current ?owing
through power supply traces and associated wiring can
cause inductive voltage transients which could exceed
R4
383k
R5
100k
UNDERVOLTAGE
6
7
12
11
V CC
SHDN
IN +
A OUT
SNS GATE
LT4356S
GND TMR
10 1
OUT
FB
EN
FLT
4356 F09
C TMR
2
9
8
R2
4.99k
CONVERTER
SHDN GND
FAULT
*SANYO 25CE22GA
100V. To minimize the voltage transients, the power trace
parasitic inductance should be minimized by using wide
traces. A small surge suppressor, D2, in Figure 9, at the
47nF
Figure 9. Overvoltage Regulator with Low-Battery Detection
input will clamp the voltage spikes.
4356fa
16
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