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参数资料
| 型号： | DC1067A-B |
| 厂商： | Linear Technology |
| 文件页数： | 2/20页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2450-1 |
| 软件下载： | QuikEval System |
| 设计资源： | DC1067A Design File DC1067A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 16 |
| 采样率（每秒）： | 30 |
| 数据接口： | 串行，SPI? |
| 已用 IC / 零件： | LTC2450-1 |
| 已供物品： | 板 |
| 相关产品： | LTC2450IDC#TRPBF-ND - IC ADC 16BIT DELTA SIG 6-DFN LTC2450IDC-1#TRPBF-ND - IC ADC 16BIT DELTA SIG 6-DFN LTC2450IDC-1#TRMPBFTR-ND - IC ADC 16BIT DELTA SIG 6-DFN LTC2450IDC#TRMPBFTR-ND - IC ADC 16BIT DELTA SIG 6-DFN LTC2450CDC-1#TRPBF-ND - IC ADC 16BIT DELTA SIG 6-DFN LTC2450CDC-1#TRMPBFTR-ND - IC ADC 16BIT DELTA SIG 6-DFN LTC2450CDC#TRPBF-ND - IC ADC 16BIT DELTA SIG 6-DFN LTC2450CDC#TRMPBFTR-ND - IC ADC 16BIT DELTA SIG 6-DFN |
LTC2450
10
2450fb
APPLICATIONS INFORMATION
Serial Clock Idle-High (CPOL = 1) Examples
In Figure 5, following a conversion cycle the LTC2450
automatically enters the low power sleep mode. The user
can monitor the conversion status at convenient intervals
using CS and SDO.
CS is pulled low to test whether or not the chip is in
the CONVERT state. While in the CONVERT state, SDO
is HIGH while CS is LOW. In the SLEEP state, SDO is
LOW while CS is LOW. These tests are not required op-
erational steps but may be useful for some applications.
When the data is available, the user applies 16 clock cycles
to transfer the result. The CS rising edge is then used to
initiate a new conversion.
The operation example of Figure 6 is identical to that of
Figure 5, except the new conversion cycle is triggered by
the falling edge of the serial clock (SCK). A 17th clock
pulse is used to trigger a new conversion cycle.
Serial Clock Idle-Low (CPOL = 0) Examples
In Figure 7, following a conversion cycle the LTC2450
automatically enters the low power sleep state. The user
determines data availability (and the end of conversion)
based upon external timing. The user then pulls CS low
(CS = ↓) and uses 16 clock cycles to transfer the result.
Following the 16th rising edge of the clock, CS is pulled high
(CS = ↑), which triggers a new conversion.
The timing diagram in Figure 8 is identical to that of Figure 7,
except in this case a new conversion is triggered by SCK.
The 16th SCK falling edge triggers a new conversion cycle
and the CS signal is subsequently pulled high.
Figure 5. Idle-High (CPOL = 1) Serial Clock Operation Example.
The Rising Edge of CS Starts a New Conversion
Figure 6. Idle-High (CPOL = 1) Clock Operation Example.
A 17th Clock Pulse is Used to Trigger a New Conversion Cycle
D15
clk1
clk2
clk3
clk4
clk15
clk16
D14
D13
D12
D2
D1
D0
SD0
SCK
CONVERT
SLEEP
LOW ICC
DATA OUTPUT
2450 F05
CS
D15
D14
D13
D12
D2
D1
D0
SD0
clk1
clk2
clk3
clk4
clk15
clk16
clk17
SCK
CONVERT
SLEEP
LOW ICC
DATA OUTPUT
2450 F06
CS
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