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参数资料
| 型号： | DC1367A |
| 厂商： | Linear Technology |
| 文件页数： | 13/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL LTM4615 |
| 软件下载： | LTM4615 |
| 设计资源： | DC1367A Design Files DC1367A Schematic |
| 标准包装： | 1 |
| 系列： | LTM®, uModule® |
| 主要目的： | DC/DC，LDO 步降 |
| 输出及类型： | 3，非隔离 |
| 输出电压： | 1.8V，1.2V，1V |
| 电流 - 输出： | 4A，2.5A，1.5A |
| 输入电压： | 2.5 ~ 5.5 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 1.25MHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | LTM4615 |
| 相关产品： | LTM4615EV#PBF-ND - IC SWIT REG BUCK 4A ADJ 144LGA LTM4615IV#PBF-ND - IC SWIT REG BUCK 4A ADJ 144LGA |
LTM4615
APPLICATIONS INFORMATION
? 4.99k = R TB
R TA =
– TRACK
V FB V FB V
4.99k R FB
R TB
TRACK1isthetrackrampappliedtotheslave’strackpin.
TRACK1 applies the track reference for the slave output up
to the point of the programmed value at which TRACK1
proceeds beyond the 0.8V reference value. The TRACK1
pin must go beyond the 0.8V to ensure the slave output
has reached its final value.
Ratiometric tracking can be achieved by a few simple
calculations and the slew rate value applied to the master’s
TRACK pin. As mentioned above, the TRACK pin has a
control range from 0V to 0.8V. The control ramp slew rate
applied to the master’s TRACK pin is directly equal to the
master’s output slew rate in Volts/Time.
The equation:
MR
SR
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in Volts/Time. When coincident
tracking is desired, then MR and SR are equal, thus R TB
is equal to 4.99k. R TA is derived from equation:
0.8V
+
where V FB is the feedback voltage reference of the regula-
tor, and V TRACK is 0.8V. Since R TB is equal to the 4.99k top
feedback resistor of the slave regulator in equal slew rate
or coincident tracking, then R TA is equal to R FB with V FB =
V TRACK . Therefore R TB = 4.99k and R TA = 10k in Figure 2.
MASTER OUTPUT
SLAVE OUTPUT
Figure 3 shows the output voltage tracking waveform for
coincident tracking.
In ratiometric tracking, a different slew rate maybe desired
for the slave regulator. R TB can be solved for when SR is
slower than MR. Make sure that the slave supply slew
rate is chosen to be fast enough so that the slave output
voltage will reach it final value before the master output.
For example, MR = 2.5V/ms and SR = 1.8V/1ms. Then
R TB = 6.98k. Solve for R TA to equal to 3.24k. The master
output must be greater than the slave output for the
tracking to work. Output load current must be present
for tracking to operate properly during power-down.
Power Good
PGOOD1 and PGOOD2 are open-drain pins that can be
used to monitor valid output voltage regulation. These
pins monitor a ±7.5% window around the regulation point.
If the output is disabled, the respective pin will go low.
COMP Pin
This pin is the external compensation pin. The module
has already been internally compensated for all output
voltages. Table 4 is provided for most application require-
ments. The LTpowerCAD Design Tool is provided for other
control loop optimization. The COMP pins must be tied
together in parallel operation.
Parallel Switching Regulator Operation
The LTM4615 switching regulators are inherently current
mode control. Paralleling will have very good current shar-
ing. This will balance the thermals on the design. Figure
13 shows a schematic of a parallel design. The voltage
feedback equation changes with the variable N as chan-
nels are paralleled.
The equation:
+ R FB
V OUT
= 0.8V ?
4.99k
N
R FB
TIME
4615 F03
N is the number of paralleled channels.
Figure 3. Output Voltage Coincident Tracking
13
For more information www.linear.com/LTM4615
4615fb
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